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Re: [PATCH v4 13/40] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2
From: |
Alex Bennée |
Subject: |
Re: [PATCH v4 13/40] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 |
Date: |
Wed, 04 Dec 2019 11:03:23 +0000 |
User-agent: |
mu4e 1.3.5; emacs 27.0.50 |
Richard Henderson <address@hidden> writes:
> This is part of a reorganization to the set of mmu_idx.
> The non-secure EL2 regime only has a single stage translation;
> there is no point in pointing out that the idx is for stage1.
>
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> target/arm/cpu.h | 4 ++--
> target/arm/internals.h | 2 +-
> target/arm/helper.c | 22 +++++++++++-----------
> target/arm/translate.c | 2 +-
> 4 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index f307de561a..28259be733 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2866,7 +2866,7 @@ static inline bool arm_excp_unmasked(CPUState *cs,
> unsigned int excp_idx,
> typedef enum ARMMMUIdx {
> ARMMMUIdx_EL10_0 = 0 | ARM_MMU_IDX_A,
> ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A,
> - ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
> + ARMMMUIdx_E2 = 2 | ARM_MMU_IDX_A,
> ARMMMUIdx_SE3 = 3 | ARM_MMU_IDX_A,
> ARMMMUIdx_SE0 = 4 | ARM_MMU_IDX_A,
> ARMMMUIdx_SE1 = 5 | ARM_MMU_IDX_A,
> @@ -2892,7 +2892,7 @@ typedef enum ARMMMUIdx {
> typedef enum ARMMMUIdxBit {
> ARMMMUIdxBit_EL10_0 = 1 << 0,
> ARMMMUIdxBit_EL10_1 = 1 << 1,
> - ARMMMUIdxBit_S1E2 = 1 << 2,
> + ARMMMUIdxBit_E2 = 1 << 2,
> ARMMMUIdxBit_SE3 = 1 << 3,
> ARMMMUIdxBit_SE0 = 1 << 4,
> ARMMMUIdxBit_SE1 = 1 << 5,
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 50d258b0e1..aee54dc105 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env,
> ARMMMUIdx mmu_idx)
> case ARMMMUIdx_EL10_1:
> case ARMMMUIdx_Stage1_E0:
> case ARMMMUIdx_Stage1_E1:
> - case ARMMMUIdx_S1E2:
> + case ARMMMUIdx_E2:
> case ARMMMUIdx_Stage2:
> case ARMMMUIdx_MPrivNegPri:
> case ARMMMUIdx_MUserNegPri:
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 98d00b4549..5172843667 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -728,7 +728,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> {
> CPUState *cs = env_cpu(env);
>
> - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
> + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
> }
>
> static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -736,7 +736,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> {
> CPUState *cs = env_cpu(env);
>
> - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
> + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
> }
>
> static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -745,7 +745,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> CPUState *cs = env_cpu(env);
> uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
>
> - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
> + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
> }
>
> static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -755,7 +755,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
>
> tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
> - ARMMMUIdxBit_S1E2);
> + ARMMMUIdxBit_E2);
> }
>
> static const ARMCPRegInfo cp_reginfo[] = {
> @@ -3189,7 +3189,7 @@ static void ats1h_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE :
> MMU_DATA_LOAD;
> uint64_t par64;
>
> - par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2);
> + par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
>
> A32_BANKED_CURRENT_REG_SET(env, par, par64);
> }
> @@ -3217,7 +3217,7 @@ static void ats_write64(CPUARMState *env, const
> ARMCPRegInfo *ri,
> mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
> break;
> case 4: /* AT S1E2R, AT S1E2W */
> - mmu_idx = ARMMMUIdx_S1E2;
> + mmu_idx = ARMMMUIdx_E2;
> break;
> case 6: /* AT S1E3R, AT S1E3W */
> mmu_idx = ARMMMUIdx_SE3;
> @@ -3954,7 +3954,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env,
> const ARMCPRegInfo *ri,
> ARMCPU *cpu = env_archcpu(env);
> CPUState *cs = CPU(cpu);
>
> - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
> + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
> }
>
> static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3980,7 +3980,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,
> const ARMCPRegInfo *ri,
> {
> CPUState *cs = env_cpu(env);
>
> - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
> + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
> }
>
> static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -4002,7 +4002,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env,
> const ARMCPRegInfo *ri,
> CPUState *cs = CPU(cpu);
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
> + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
> }
>
> static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -4055,7 +4055,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env,
> const ARMCPRegInfo *ri,
> uint64_t pageaddr = sextract64(value << 12, 0, 56);
>
> tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
> - ARMMMUIdxBit_S1E2);
> + ARMMMUIdxBit_E2);
> }
>
> static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -8565,7 +8565,7 @@ static inline uint32_t regime_el(CPUARMState *env,
> ARMMMUIdx mmu_idx)
> {
> switch (mmu_idx) {
> case ARMMMUIdx_Stage2:
> - case ARMMMUIdx_S1E2:
> + case ARMMMUIdx_E2:
> return 2;
> case ARMMMUIdx_SE3:
> return 3;
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 6cf2fe2806..51ea99e6f9 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *s)
> * otherwise, access as if at PL0.
> */
> switch (s->mmu_idx) {
> - case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */
> + case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */
> case ARMMMUIdx_EL10_0:
> case ARMMMUIdx_EL10_1:
> return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0);
--
Alex Bennée
- Re: [PATCH v4 06/40] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask, (continued)
- [PATCH v4 13/40] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2019/12/02
- Re: [PATCH v4 13/40] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2,
Alex Bennée <=
- [PATCH v4 07/40] target/arm: Simplify tlb_force_broadcast alternatives, Richard Henderson, 2019/12/02
- [PATCH v4 09/40] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2019/12/02
- [PATCH v4 10/40] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2019/12/02
- [PATCH v4 12/40] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2019/12/02