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[Qemu-devel] [PATCH v3 14/15] target/sparc: Add TLB entry with attribute
From: |
tony.nguyen |
Subject: |
[Qemu-devel] [PATCH v3 14/15] target/sparc: Add TLB entry with attributes |
Date: |
Thu, 25 Jul 2019 07:11:40 +0000 |
Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.
Signed-off-by: Tony Nguyen <address@hidden>
---
target/sparc/mmu_helper.c | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index cbd1e91..826e14b 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -88,7 +88,7 @@ static const int perm_table[2][8] = {
};
static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
- int *prot, int *access_index,
+ int *prot, int *access_index, MemTxAttrs
*attrs,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
@@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
target_ulong vaddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
+ MemTxAttrs attrs = {};
/*
* TODO: If we ever need tlb_vaddr_to_host for this target,
@@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
assert(!probe);
address &= TARGET_PAGE_MASK;
- error_code = get_physical_address(env, &paddr, &prot, &access_index,
+ error_code = get_physical_address(env, &paddr, &prot, &access_index,
&attrs,
address, access_type,
mmu_idx, &page_size);
vaddr = address;
@@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
return 0;
}
-static int get_physical_address_data(CPUSPARCState *env,
- hwaddr *physical, int *prot,
+static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
+ int *prot, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx)
{
CPUState *cs = env_cpu(env);
@@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env,
return 1;
}
-static int get_physical_address_code(CPUSPARCState *env,
- hwaddr *physical, int *prot,
+static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
+ int *prot, MemTxAttrs *attrs,
target_ulong address, int mmu_idx)
{
CPUState *cs = env_cpu(env);
@@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env,
}
static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
- int *prot, int *access_index,
+ int *prot, int *access_index, MemTxAttrs
*attrs,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
@@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env,
hwaddr *physical,
}
if (rw == 2) {
- return get_physical_address_code(env, physical, prot, address,
+ return get_physical_address_code(env, physical, prot, attrs, address,
mmu_idx);
} else {
- return get_physical_address_data(env, physical, prot, address, rw,
- mmu_idx);
+ return get_physical_address_data(env, physical, prot, attrs, address,
+ rw, mmu_idx);
}
}
@@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
target_ulong vaddr;
hwaddr paddr;
target_ulong page_size;
+ MemTxAttrs attrs = {};
int error_code = 0, prot, access_index;
address &= TARGET_PAGE_MASK;
- error_code = get_physical_address(env, &paddr, &prot, &access_index,
+ error_code = get_physical_address(env, &paddr, &prot, &access_index,
&attrs,
address, access_type,
mmu_idx, &page_size);
if (likely(error_code == 0)) {
@@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
env->dmmu.mmu_primary_context,
env->dmmu.mmu_secondary_context);
- tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,
+ page_size);
return true;
}
if (probe) {
@@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env,
hwaddr *phys,
{
target_ulong page_size;
int prot, access_index;
+ MemTxAttrs attrs = {};
- return get_physical_address(env, phys, &prot, &access_index, addr, rw,
- mmu_idx, &page_size);
+ return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
+ rw, mmu_idx, &page_size);
}
#if defined(TARGET_SPARC64)
--
1.8.3.1
- [Qemu-devel] [PATCH v3 04/15] hw/s390x: Access MemoryRegion with MemOp, (continued)
- [Qemu-devel] [PATCH v3 04/15] hw/s390x: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 05/15] hw/intc/armv7m_nic: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 06/15] hw/virtio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 07/15] hw/vfio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 08/15] exec: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 09/15] cputlb: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 10/15] memory: Access MemoryRegion with MemOp semantics, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 11/15] memory: Single byte swap along the I/O path, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attribute, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 14/15] target/sparc: Add TLB entry with attributes,
tony.nguyen <=
- [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit, tony.nguyen, 2019/07/25
- Re: [Qemu-devel] [PATCH v3 00/15] Invert Endian bit in SPARCv9 MMU TTE, no-reply, 2019/07/25
- [Qemu-devel] [PATCH v4 00/15] Invert Endian bit in SPARCv9 MMU TTE, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 02/15] memory: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 03/15] target/mips: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 04/15] hw/s390x: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 01/15] tcg: TCGMemOp is now accelerator independent MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 05/15] hw/intc/armv7m_nic: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 06/15] hw/virtio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 07/15] hw/vfio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25