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[Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attri
From: |
tony.nguyen |
Subject: |
[Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attribute |
Date: |
Thu, 25 Jul 2019 07:11:11 +0000 |
Notice new attribute, byte swap, and force the transaction through the
memory slow path.
Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.
Signed-off-by: Tony Nguyen <address@hidden>
---
accel/tcg/cputlb.c | 11 +++++++++++
include/exec/memattrs.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index e61b1eb..f292a87 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
vaddr,
*/
address |= TLB_RECHECK;
}
+ if (attrs.byte_swap) {
+ address |= TLB_FORCE_SLOW;
+ }
if (!memory_region_is_ram(section->mr) &&
!memory_region_is_romd(section->mr)) {
/* IO memory case */
@@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
bool locked = false;
MemTxResult r;
+ if (iotlbentry->attrs.byte_swap) {
+ op ^= MO_BSWAP;
+ }
+
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
@@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
bool locked = false;
MemTxResult r;
+ if (iotlbentry->attrs.byte_swap) {
+ op ^= MO_BSWAP;
+ }
+
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a3477..a0644eb 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
unsigned int user:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
+ /* SPARC64: TTE invert endianness */
+ unsigned int byte_swap:1;
/*
* The following are target-specific page-table bits. These are not
* related to actual memory transactions at all. However, this structure
--
1.8.3.1
- [Qemu-devel] [PATCH v3 03/15] target/mips: Access MemoryRegion with MemOp, (continued)
- [Qemu-devel] [PATCH v3 03/15] target/mips: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 04/15] hw/s390x: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 05/15] hw/intc/armv7m_nic: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 06/15] hw/virtio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 07/15] hw/vfio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 08/15] exec: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 09/15] cputlb: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 10/15] memory: Access MemoryRegion with MemOp semantics, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 11/15] memory: Single byte swap along the I/O path, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attribute,
tony.nguyen <=
- [Qemu-devel] [PATCH v3 14/15] target/sparc: Add TLB entry with attributes, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit, tony.nguyen, 2019/07/25
- Re: [Qemu-devel] [PATCH v3 00/15] Invert Endian bit in SPARCv9 MMU TTE, no-reply, 2019/07/25
- [Qemu-devel] [PATCH v4 00/15] Invert Endian bit in SPARCv9 MMU TTE, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 02/15] memory: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 03/15] target/mips: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 04/15] hw/s390x: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 01/15] tcg: TCGMemOp is now accelerator independent MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 05/15] hw/intc/armv7m_nic: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 06/15] hw/virtio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25