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[Qemu-devel] [PATCH v3 08/15] exec: Access MemoryRegion with MemOp
From: |
tony.nguyen |
Subject: |
[Qemu-devel] [PATCH v3 08/15] exec: Access MemoryRegion with MemOp |
Date: |
Thu, 25 Jul 2019 07:08:34 +0000 |
Signed-off-by: Tony Nguyen <address@hidden>
---
exec.c | 6 ++++--
memory_ldst.inc.c | 18 +++++++++---------
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/exec.c b/exec.c
index 3e78de3..5013864 100644
--- a/exec.c
+++ b/exec.c
@@ -3334,7 +3334,8 @@ static MemTxResult flatview_write_continue(FlatView *fv,
hwaddr addr,
/* XXX: could force current_cpu to NULL to avoid
potential bugs */
val = ldn_p(buf, l);
- result |= memory_region_dispatch_write(mr, addr1, val, l, attrs);
+ result |= memory_region_dispatch_write(mr, addr1, val,
+ SIZE_MEMOP(l), attrs);
} else {
/* RAM case */
ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
@@ -3395,7 +3396,8 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr
addr,
/* I/O case */
release_lock |= prepare_mmio_access(mr);
l = memory_access_size(mr, l, addr1);
- result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs);
+ result |= memory_region_dispatch_read(mr, addr1, &val,
+ SIZE_MEMOP(l), attrs);
stn_p(buf, l, val);
} else {
/* RAM case */
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index acf865b..e073cf9 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -38,7 +38,7 @@ static inline uint32_t glue(address_space_ldl_internal,
SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, SIZE_MEMOP(4), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap32(val);
@@ -114,7 +114,7 @@ static inline uint64_t glue(address_space_ldq_internal,
SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, SIZE_MEMOP(8), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap64(val);
@@ -188,7 +188,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 1, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, SIZE_MEMOP(1), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -224,7 +224,7 @@ static inline uint32_t glue(address_space_lduw_internal,
SUFFIX)(ARG1_DECL,
release_lock |= prepare_mmio_access(mr);
/* I/O case */
- r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs);
+ r = memory_region_dispatch_read(mr, addr1, &val, SIZE_MEMOP(2), attrs);
#if defined(TARGET_WORDS_BIGENDIAN)
if (endian == DEVICE_LITTLE_ENDIAN) {
val = bswap16(val);
@@ -300,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
if (l < 4 || !memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, SIZE_MEMOP(4), attrs);
} else {
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
stl_p(ptr, val);
@@ -346,7 +346,7 @@ static inline void glue(address_space_stl_internal,
SUFFIX)(ARG1_DECL,
val = bswap32(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, SIZE_MEMOP(4), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -408,7 +408,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (!memory_access_is_direct(mr, true)) {
release_lock |= prepare_mmio_access(mr);
- r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, SIZE_MEMOP(1), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -451,7 +451,7 @@ static inline void glue(address_space_stw_internal,
SUFFIX)(ARG1_DECL,
val = bswap16(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 2, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, SIZE_MEMOP(2), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -524,7 +524,7 @@ static void glue(address_space_stq_internal,
SUFFIX)(ARG1_DECL,
val = bswap64(val);
}
#endif
- r = memory_region_dispatch_write(mr, addr1, val, 8, attrs);
+ r = memory_region_dispatch_write(mr, addr1, val, SIZE_MEMOP(8), attrs);
} else {
/* RAM case */
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
--
1.8.3.1
- [Qemu-devel] [PATCH v2 16/20] memory: Single byte swap along the I/O path, (continued)
- [Qemu-devel] [PATCH v2 16/20] memory: Single byte swap along the I/O path, tony.nguyen, 2019/07/22
- [Qemu-devel] [PATCH v2 17/20] cpu: TLB_FLAGS_MASK bit to force memory slow path, tony.nguyen, 2019/07/22
- [Qemu-devel] [PATCH v3 00/15] Invert Endian bit in SPARCv9 MMU TTE, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 02/15] memory: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 01/15] tcg: TCGMemOp is now accelerator independent MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 03/15] target/mips: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 04/15] hw/s390x: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 05/15] hw/intc/armv7m_nic: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 06/15] hw/virtio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 07/15] hw/vfio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 08/15] exec: Access MemoryRegion with MemOp,
tony.nguyen <=
- [Qemu-devel] [PATCH v3 09/15] cputlb: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 10/15] memory: Access MemoryRegion with MemOp semantics, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 11/15] memory: Single byte swap along the I/O path, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attribute, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 14/15] target/sparc: Add TLB entry with attributes, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v3 15/15] target/sparc: sun4u Invert Endian TTE bit, tony.nguyen, 2019/07/25
- Re: [Qemu-devel] [PATCH v3 00/15] Invert Endian bit in SPARCv9 MMU TTE, no-reply, 2019/07/25
- [Qemu-devel] [PATCH v4 00/15] Invert Endian bit in SPARCv9 MMU TTE, tony.nguyen, 2019/07/25
- [Qemu-devel] [PATCH v4 02/15] memory: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25