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[Qemu-devel] [PATCH v17 00/24] Add RX archtecture support
From: |
Yoshinori Sato |
Subject: |
[Qemu-devel] [PATCH v17 00/24] Add RX archtecture support |
Date: |
Fri, 7 Jun 2019 18:10:52 +0900 |
Hello.
This patch series is added Renesas RX target emulation.
Changes v17.
Remove cpu class name suffix.
My git repository is bellow.
git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190607
Testing binaries bellow.
u-boot
Download - https://osdn.net/users/ysato/pf/qemu/dl/u-boot.bin.gz
starting
$ gzip -d u-boot.bin.gz
$ qemu-system-rx -bios u-boot.bin
linux and pico-root (only sash)
Download - https://osdn.net/users/ysato/pf/qemu/dl/zImage (kernel)
https://osdn.net/users/ysato/pf/qemu/dl/rx-qemu.dtb (DeviceTree)
starting
$ qemu-system-rx -kernel zImage -dtb rx-qemu.dtb -append "earlycon"
Richard Henderson (11):
target/rx: Convert to CPUClass::tlb_fill
target/rx: Add RX to SysEmuTarget
target/rx: Fix cpu types and names
tests: Add rx to machine-none-test.c
hw/rx: Honor -accel qtest
target/rx: Disassemble rx_index_addr into a string
target/rx: Replace operand with prt_ldmi in disassembler
target/rx: Use prt_ldmi for XCHG_mr disassembly
target/rx: Emit all disassembly in one prt()
target/rx: Collect all bytes during disassembly
target/rx: Dump bytes for each insn during disassembly
Yoshinori Sato (13):
target/rx: TCG translation
target/rx: TCG helper
target/rx: CPU definition
target/rx: RX disassembler
hw/intc: RX62N interrupt controller (ICUa)
hw/timer: RX62N internal timer modules
hw/char: RX62N serial communication interface (SCI)
hw/rx: RX Target hardware definition
qemu/bitops.h: Add extract8 and extract16
hw/registerfields.h: Add 8bit and 16bit register macros
Add rx-softmmu
MAINTAINERS: Add RX
target/rx: Remove suffix in cpu class.
configure | 8 +
default-configs/rx-softmmu.mak | 3 +
qapi/common.json | 3 +-
include/disas/dis-asm.h | 5 +
include/hw/char/renesas_sci.h | 45 +
include/hw/intc/rx_icu.h | 56 +
include/hw/registerfields.h | 32 +-
include/hw/rx/rx.h | 7 +
include/hw/rx/rx62n.h | 94 ++
include/hw/timer/renesas_cmt.h | 38 +
include/hw/timer/renesas_tmr.h | 53 +
include/qemu/bitops.h | 38 +
include/sysemu/arch_init.h | 1 +
target/rx/cpu.h | 226 ++++
target/rx/helper.h | 31 +
arch_init.c | 2 +
hw/char/renesas_sci.c | 340 ++++++
hw/intc/rx_icu.c | 376 +++++++
hw/rx/rx-virt.c | 105 ++
hw/rx/rx62n.c | 246 ++++
hw/timer/renesas_cmt.c | 275 +++++
hw/timer/renesas_tmr.c | 455 ++++++++
target/rx/cpu.c | 241 ++++
target/rx/disas.c | 1446 ++++++++++++++++++++++++
target/rx/gdbstub.c | 112 ++
target/rx/helper.c | 148 +++
target/rx/monitor.c | 38 +
target/rx/op_helper.c | 470 ++++++++
target/rx/translate.c | 2432 ++++++++++++++++++++++++++++++++++++++++
tests/machine-none-test.c | 1 +
MAINTAINERS | 19 +
hw/Kconfig | 1 +
hw/char/Kconfig | 3 +
hw/char/Makefile.objs | 1 +
hw/intc/Kconfig | 3 +
hw/intc/Makefile.objs | 1 +
hw/rx/Kconfig | 14 +
hw/rx/Makefile.objs | 2 +
hw/timer/Kconfig | 6 +
hw/timer/Makefile.objs | 3 +
target/rx/Makefile.objs | 12 +
target/rx/insns.decode | 621 ++++++++++
42 files changed, 8011 insertions(+), 2 deletions(-)
create mode 100644 default-configs/rx-softmmu.mak
create mode 100644 include/hw/char/renesas_sci.h
create mode 100644 include/hw/intc/rx_icu.h
create mode 100644 include/hw/rx/rx.h
create mode 100644 include/hw/rx/rx62n.h
create mode 100644 include/hw/timer/renesas_cmt.h
create mode 100644 include/hw/timer/renesas_tmr.h
create mode 100644 target/rx/cpu.h
create mode 100644 target/rx/helper.h
create mode 100644 hw/char/renesas_sci.c
create mode 100644 hw/intc/rx_icu.c
create mode 100644 hw/rx/rx-virt.c
create mode 100644 hw/rx/rx62n.c
create mode 100644 hw/timer/renesas_cmt.c
create mode 100644 hw/timer/renesas_tmr.c
create mode 100644 target/rx/cpu.c
create mode 100644 target/rx/disas.c
create mode 100644 target/rx/gdbstub.c
create mode 100644 target/rx/helper.c
create mode 100644 target/rx/monitor.c
create mode 100644 target/rx/op_helper.c
create mode 100644 target/rx/translate.c
create mode 100644 hw/rx/Kconfig
create mode 100644 hw/rx/Makefile.objs
create mode 100644 target/rx/Makefile.objs
create mode 100644 target/rx/insns.decode
--
2.11.0
- [Qemu-devel] [PATCH v17 00/24] Add RX archtecture support,
Yoshinori Sato <=
- [Qemu-devel] [PATCH v17 22/24] target/rx: Collect all bytes during disassembly, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 07/24] hw/char: RX62N serial communication interface (SCI), Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 12/24] target/rx: Add RX to SysEmuTarget, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 11/24] target/rx: Convert to CPUClass::tlb_fill, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 10/24] hw/registerfields.h: Add 8bit and 16bit register macros, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 14/24] tests: Add rx to machine-none-test.c, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 24/24] target/rx: Remove suffix in cpu class., Yoshinori Sato, 2019/06/07