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[Qemu-devel] [PATCH v17 10/24] hw/registerfields.h: Add 8bit and 16bit r
From: |
Yoshinori Sato |
Subject: |
[Qemu-devel] [PATCH v17 10/24] hw/registerfields.h: Add 8bit and 16bit register macros |
Date: |
Fri, 7 Jun 2019 18:11:02 +0900 |
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
include/hw/registerfields.h | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 2659a58737..a0bb0654d6 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -22,6 +22,14 @@
enum { A_ ## reg = (addr) }; \
enum { R_ ## reg = (addr) / 4 };
+#define REG8(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) };
+
+#define REG16(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 2 };
+
/* Define SHIFT, LENGTH and MASK constants for a field within a register */
/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -34,6 +42,12 @@
MAKE_64BIT_MASK(shift, length)};
/* Extract a field from a register */
+#define FIELD_EX8(storage, reg, field) \
+ extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
+#define FIELD_EX16(storage, reg, field) \
+ extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH)
#define FIELD_EX32(storage, reg, field) \
extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH)
@@ -49,6 +63,22 @@
* Assigning values larger then the target field will result in
* compilation warnings.
*/
+#define FIELD_DP8(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint8_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
+#define FIELD_DP16(storage, reg, field, val) ({ \
+ struct { \
+ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
+ } v = { .v = val }; \
+ uint16_t d; \
+ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
+ R_ ## reg ## _ ## field ## _LENGTH, v.v); \
+ d; })
#define FIELD_DP32(storage, reg, field, val) ({ \
struct { \
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
@@ -57,7 +87,7 @@
d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH, v.v); \
d; })
-#define FIELD_DP64(storage, reg, field, val) ({ \
+#define FIELD_DP64(storage, reg, field, val) ({ \
struct { \
unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
} v = { .v = val }; \
--
2.11.0
- [Qemu-devel] [PATCH v17 00/24] Add RX archtecture support, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 22/24] target/rx: Collect all bytes during disassembly, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 07/24] hw/char: RX62N serial communication interface (SCI), Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 12/24] target/rx: Add RX to SysEmuTarget, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 11/24] target/rx: Convert to CPUClass::tlb_fill, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 10/24] hw/registerfields.h: Add 8bit and 16bit register macros,
Yoshinori Sato <=
- [Qemu-devel] [PATCH v17 14/24] tests: Add rx to machine-none-test.c, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 24/24] target/rx: Remove suffix in cpu class., Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 18/24] target/rx: Disassemble rx_index_addr into a string, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 08/24] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 04/24] target/rx: RX disassembler, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 23/24] target/rx: Dump bytes for each insn during disassembly, Yoshinori Sato, 2019/06/07
- [Qemu-devel] [PATCH v17 05/24] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/06/07