Re: [Qemu-devel] i386: EFER vs 32-bit CPU

[Peter Xu]

On Thu, May 30, 2019 at 08:54:38AM +0300, Pavel Dovgalyuk wrote:
> > From: Peter Xu [mailto:address@hidden
> > On Wed, May 29, 2019 at 02:26:39PM +0300, Pavel Dovgalyuk wrote:
> > > Hello!
> > >
> > >
> > >
> > > I found this while debugging the inconsistent saved/restored state of the 
> > > virtual machine.
> > >
> > >
> > >
> > > i386 (32 bit) emulation uses this register (in wrmsr and in MMU fault 
> > > processing).
> > 
> > Sorry if this question is elementary, but... why would a 32bit guest
> > use IA32_EFER?  From SDM I only see 4 bits defined in this MSR (SCE,
> > LME, LMA, NXE) but is there any of them that should be set in a 32bit
> > guest?
> 
> Ubuntu server 16.04 (32 bit) sets NXE while booting.
> NXE affects the MMU fault processing and exception generation.

But this is what I read from the spec (SDM 4.6.1):

Instruction fetches:

  - Access rights depend on the mode of the linear address, the paging
    mode, and the value of IA32_EFER.NXE:

    - For 32-bit paging or if IA32_EFER.NXE = 0, instructions may be
      fetched from any user-mode address.

    - For PAE paging or 4-level paging with IA32_EFER.NXE = 1,
      instructions may be fetched from any user-mode address with a
      translation for which the XD flag is 0 in every paging-structure
      entry controlling the translation.

    - Instructions may not be fetched from any supervisor-mode address.

I'm not an expert of x86 arch but it seems to me that no matter what
NXE bit should be meaningless on x86 32bit according to above.

Also, above spec seems to match with the kvm code too, since in
init_kvm_tdp_mmu() where kvm_mmu.nx is only set with either long mode
or PAE, but never 32bit.  So I'm a bit confused on why that should be
migrated for 32bit (or even, whether should EFER MSR be visible to
such a guest at all?).

Regards,

-- 
Peter Xu