[Qemu-devel] [PATCH] Incorrect Stack Pointer shadow register support on some m68k CPUs

[Lucien Murray-Pitts]

On CPU32 and the early 68000 and 68010 the ISP doesnt exist.
These CPUs only have SSP/USP.

The availability of this feature is determined by the
implementation of Master mode bit in the SR register.

Those with the master-mode bit have ISP.

Additional comments added to the features set to claify
exactly what differentiates each class.  (m68k_features)

The movec instruction when accessing these shadow registers
in some configurations should issue a TRAP.  This patch does not
add this funcitonality to the helpers.

Signed-off-by: Lucien Murray-Pitts <address@hidden>
---
 target/m68k/cpu.c    |  1 +
 target/m68k/cpu.h    | 12 ++++++++++--
 target/m68k/helper.c |  3 ++-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index b16957934a..61368d1a9a 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -121,6 +121,7 @@ static void m68020_cpu_initfn(Object *obj)
     CPUM68KState *env = &cpu->env;
 
     m68k_set_feature(env, M68K_FEATURE_M68000);
+    m68k_set_feature(env, M68K_FEATURE_MSP);
     m68k_set_feature(env, M68K_FEATURE_USP);
     m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
     m68k_set_feature(env, M68K_FEATURE_QUAD_MULDIV);
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 9deff9e234..8be68e5e4f 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -462,12 +462,19 @@ void m68k_switch_sp(CPUM68KState *env);
 
 void do_m68k_semihosting(CPUM68KState *env, int nr);
 
-/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
+/* The ColdFire core ISA is a RISC-style reduction of the 68000 series
+   Whilst the 68000 flourished by adding extended stack/instructions in
+   five main flavors original 68000, 680010/20/30/40, and a CPU32/CPU32+
+
+   CPU32/32+ are basically 68000/10 compatible, with and 68020.  Mostly
+   Supervisor state differences.
+
+   There are 4 ColdFire core ISA revisions: A, A+, B and C.
    Each feature covers the subset of instructions common to the
    ISA revisions mentioned.  */
 
 enum m68k_features {
-    M68K_FEATURE_M68000,
+    M68K_FEATURE_M68000,   /* Base m68k set, as opposed to ColdFire */
     M68K_FEATURE_CF_ISA_A,
     M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
     M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
@@ -477,6 +484,7 @@ enum m68k_features {
     M68K_FEATURE_CF_EMAC,
     M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
     M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
+    M68K_FEATURE_MSP, /* Master Stack Pointer. Not 68000/10,Coldfire,CPU32 */
     M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
     M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
     M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 6db93bdd81..64c8a82a92 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -337,7 +337,8 @@ void m68k_switch_sp(CPUM68KState *env)
     env->sp[env->current_sp] = env->aregs[7];
     if (m68k_feature(env, M68K_FEATURE_M68000)) {
         if (env->sr & SR_S) {
-            if (env->sr & SR_M) {
+            /* SR:Master-Mode bit unimplemented then ISP is not available */
+            if (!m68k_feature(env, M68K_FEATURE_MSP) || env->sr & SR_M) {
                 new_sp = M68K_SSP;
             } else {
                 new_sp = M68K_ISP;
-- 
2.21.0