[Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1

[Palmer Dabbelt]

The following changes since commit a7b21f6762a2d6ec08106d8a7ccb11829914523f:

  Merge remote-tracking branch 
'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging (2019-05-24 
12:47:49 +0100)

are available in the Git repository at:

  git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf0

for you to fetch changes up to 1e0d985fa9136a563168a3da66f3d17820404ee2:

  target/riscv: Only flush TLB if SATP.ASID changes (2019-05-24 12:09:25 -0700)

----------------------------------------------------------------
RISC-V Patches for the 4.1 Soft Freeze, Part 1

This tag contains a handful of patches that I'd like to target for 4.1:

* An emulation for SiFive's GPIO device.
* A fix to disallow sfence.vma from userspace.
* Additional decodetree cleanups that should have no functional impact.
* C extension emulation fidelity fixes that were noticed as part of that
  cleanup process.
* A new "spike" target, along with the deprecation of a handful of old
  targets and CPUs.
* Some initial infastructure related to the hypervisor extension.
* An emulation fidelity fix that prevents prevents arbitrary bits in the
  SIP CSR from being set.
* A small performance improvement that avoids excessive TLB flushing
  when the ASID does not change.

This time I've used a new testing workflow: I've tested on both 32-bit
and 64-bit builds of OpenEmbedded, via the default OpenSBI-based boot
flow.

----------------------------------------------------------------
Alistair Francis (14):
      linux-user/riscv: Add the CPU type as a comment
      riscv: virt: Allow specifying a CPU via commandline
      target/riscv: Create settable CPU properties
      target/riscv: Add a base 32 and 64 bit CPU
      target/riscv: Deprecate the generic no MMU CPUs
      riscv: spike: Add a generic spike machine
      target/riscv: Mark privilege level 2 as reserved
      target/riscv: Trigger interrupt on MIP update asynchronously
      target/riscv: Improve the scause logic
      target/riscv: Add the MPV and MTL mstatus bits
      target/riscv: Allow setting mstatus virtulisation bits
      target/riscv: Add Hypervisor CSR macros
      target/riscv: Add the HSTATUS register masks
      target/riscv: Add the HGATP register masks

Fabien Chouteau (2):
      SiFive RISC-V GPIO Device
      RISC-V: fix single stepping over ret and other branching instructions

Jonathan Behrens (4):
      target/riscv: Do not allow sfence.vma from user mode
      target/riscv: Remove unused include of riscv_htif.h for virt board riscv
      target/riscv: More accurate handling of `sip` CSR
      target/riscv: Only flush TLB if SATP.ASID changes

Richard Henderson (9):
      target/riscv: Name the argument sets for all of insn32 formats
      target/riscv: Use --static-decode for decodetree
      target/riscv: Merge argument sets for insn32 and insn16
      target/riscv: Merge argument decode for RVC shifti
      target/riscv: Use pattern groups in insn16.decode
      target/riscv: Split RVC32 and RVC64 insns into separate files
      target/riscv: Split gen_arith_imm into functional and temp
      target/riscv: Remove spaces from register names
      target/riscv: Add checks for several RVC reserved operands

 Makefile.objs                                  |   1 +
 hw/riscv/Makefile.objs                         |   1 +
 hw/riscv/sifive_e.c                            |  28 +-
 hw/riscv/sifive_gpio.c                         | 388 +++++++++++++++++++++++++
 hw/riscv/spike.c                               | 106 ++++++-
 hw/riscv/trace-events                          |   7 +
 hw/riscv/virt.c                                |   4 +-
 include/hw/riscv/sifive_e.h                    |   8 +-
 include/hw/riscv/sifive_gpio.h                 |  72 +++++
 include/hw/riscv/virt.h                        |   4 +-
 linux-user/riscv/target_elf.h                  |   1 +
 qemu-deprecated.texi                           |  21 ++
 target/riscv/Makefile.objs                     |  15 +-
 target/riscv/cpu.c                             |  79 ++++-
 target/riscv/cpu.h                             |  10 +
 target/riscv/cpu_bits.h                        |  45 ++-
 target/riscv/cpu_helper.c                      |  35 ++-
 target/riscv/csr.c                             |  30 +-
 target/riscv/insn16-32.decode                  |  28 ++
 target/riscv/insn16-64.decode                  |  36 +++
 target/riscv/insn16.decode                     | 173 +++++------
 target/riscv/insn32.decode                     |  10 +-
 target/riscv/insn_trans/trans_privileged.inc.c |   8 +-
 target/riscv/insn_trans/trans_rvc.inc.c        | 347 ----------------------
 target/riscv/insn_trans/trans_rvi.inc.c        |  26 +-
 target/riscv/op_helper.c                       |   7 +-
 target/riscv/translate.c                       |  77 ++++-
 27 files changed, 1053 insertions(+), 514 deletions(-)
 create mode 100644 hw/riscv/sifive_gpio.c
 create mode 100644 hw/riscv/trace-events
 create mode 100644 include/hw/riscv/sifive_gpio.h
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode
 delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c