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[Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPU
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From: |
Palmer Dabbelt |
|
Subject: |
[Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs |
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Date: |
Sat, 25 May 2019 18:09:36 -0700 |
From: Alistair Francis <address@hidden>
These can now be specified via the command line so we no longer need
these.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
qemu-deprecated.texi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index fbdde3d1b4af..9dca81f461e3 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -147,6 +147,12 @@ four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``,
``rv64gcsu-v1.9.1`` an
``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU
``priv_spec``
option when using the ``rv32`` or ``rv64`` CPUs.
address@hidden RISC-V ISA CPUs (since 4.1)
+
+The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu``
and
+``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be
specified
+via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
+
@section System emulator devices
@subsection bluetooth (since 3.1)
--
2.21.0
- [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 26/29] target/riscv: Add the HGATP register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 25/29] target/riscv: Add the HSTATUS register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 24/29] target/riscv: Add Hypervisor CSR macros, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 21/29] target/riscv: Improve the scause logic, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 18/29] riscv: spike: Add a generic spike machine, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25