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[Qemu-devel] [PULL 23/29] target/riscv: Allow setting mstatus virtulisat
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits |
Date: |
Sat, 25 May 2019 18:09:42 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Revieweb-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/csr.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f9d8d150e012..e6d68a99560d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -290,7 +290,6 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
target_ulong mstatus = env->mstatus;
target_ulong mask = 0;
- target_ulong mpp = get_field(val, MSTATUS_MPP);
/* flush tlb on mstatus fields that affect VM */
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
@@ -305,7 +304,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
MSTATUS_VM : 0);
}
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
MSTATUS_MPRV | MSTATUS_SUM)) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
}
@@ -313,13 +312,13 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW;
- }
-
- /* silenty discard mstatus.mpp writes for unsupported modes */
- if (mpp == PRV_H ||
- (!riscv_has_ext(env, RVS) && mpp == PRV_S) ||
- (!riscv_has_ext(env, RVU) && mpp == PRV_U)) {
- mask &= ~MSTATUS_MPP;
+#if defined(TARGET_RISCV64)
+ /*
+ * RV32: MPV and MTL are not in mstatus. The current plan is to
+ * add them to mstatush. For now, we just don't support it.
+ */
+ mask |= MSTATUS_MPP | MSTATUS_MPV;
+#endif
}
mstatus = (mstatus & ~mask) | (val & mask);
--
2.21.0
- [Qemu-devel] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes, (continued)
- [Qemu-devel] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 26/29] target/riscv: Add the HGATP register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 25/29] target/riscv: Add the HSTATUS register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 24/29] target/riscv: Add Hypervisor CSR macros, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 21/29] target/riscv: Improve the scause logic, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 18/29] riscv: spike: Add a generic spike machine, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 06/29] target/riscv: Merge argument sets for insn32 and insn16, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats, Palmer Dabbelt, 2019/05/25
- [Qemu-devel] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions, Palmer Dabbelt, 2019/05/25