Re: [Qemu-devel] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL

[Richard Henderson]

On 4/16/19 5:57 AM, Peter Maydell wrote:
> The M-profile CONTROL register has two bits -- SFPA and FPCA --
> which relate to floating-point support, and should be RES0 otherwise.
> Handle them correctly in the MSR/MRS register access code.
> Neither is banked between security states, so they are stored
> in v7m.control[M_REG_S] regardless of current security state.
> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++-------
>  1 file changed, 49 insertions(+), 8 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


r~