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[Qemu-devel] [PATCH 07/26] target/arm: Clear CONTROL_S.SFPA in SG insn i
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 07/26] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present |
Date: |
Tue, 16 Apr 2019 13:57:25 +0100 |
If the floating point extension is present, then the SG instruction
must clear the CONTROL_S.SFPA bit. Implement this.
(On a no-FPU system the bit will always be zero, so we don't need
to make the clearing of the bit conditional on ARM_FEATURE_VFP.)
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 27e5f98bc73..b4f1609a1c6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8809,6 +8809,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
", executing it\n", env->regs[15]);
env->regs[14] &= ~1;
+ env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
switch_v7m_security_state(env, true);
xpsr_write(env, 0, XPSR_IT);
env->regs[15] += 4;
--
2.20.1
- [Qemu-devel] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable, (continued)
- [Qemu-devel] [PATCH 01/26] target/arm: Make sure M-profile FPSCR RES0 bits are not settable, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 03/26] target/arm: Implement dummy versions of M-profile FP-related registers, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 02/26] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 04/26] target/arm: Disable most VFP sysregs for M-profile, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 06/26] target/arm: Decode FP instructions for M profile, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 07/26] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present,
Peter Maydell <=
- [Qemu-devel] [PATCH 09/26] target/arm/helper: don't return early for STKOF faults during stacking, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 10/26] target/arm: Handle floating point registers in exception entry, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 05/26] target/arm: Honour M-profile FP enable bits, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 08/26] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 11/26] target/arm: Implement v7m_update_fpccr(), Peter Maydell, 2019/04/16