[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 30/62] ppc/pnv: fix logging primitives using Ox
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 30/62] ppc/pnv: fix logging primitives using Ox |
Date: |
Tue, 12 Mar 2019 19:54:30 +1100 |
From: Cédric Le Goater <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_lpc.c | 10 +++++-----
hw/ppc/pnv_psi.c | 4 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 172a915cfc..9b18ce55e3 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -294,7 +294,7 @@ static uint64_t lpc_hc_read(void *opaque, hwaddr addr,
unsigned size)
val = lpc->lpc_hc_error_addr;
break;
default:
- qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
+ qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
HWADDR_PRIx "\n", addr);
}
return val;
@@ -332,7 +332,7 @@ static void lpc_hc_write(void *opaque, hwaddr addr,
uint64_t val,
case LPC_HC_ERROR_ADDRESS:
break;
default:
- qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
+ qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
HWADDR_PRIx "\n", addr);
}
}
@@ -370,7 +370,7 @@ static uint64_t opb_master_read(void *opaque, hwaddr addr,
unsigned size)
val = lpc->opb_irq_input;
break;
default:
- qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
+ qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
HWADDR_PRIx "\n", addr);
}
@@ -399,8 +399,8 @@ static void opb_master_write(void *opaque, hwaddr addr,
/* Read only */
break;
default:
- qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
- HWADDR_PRIx "\n", addr);
+ qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
+ HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
}
}
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 44bc0cbf58..c872be0b9c 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -323,7 +323,7 @@ static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t
offset, bool mmio)
val = psi->regs[offset];
break;
default:
- qemu_log_mask(LOG_UNIMP, "PSI: read at Ox%" PRIx32 "\n", offset);
+ qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
}
return val;
}
@@ -382,7 +382,7 @@ static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset,
uint64_t val,
pnv_psi_set_irsn(psi, val);
break;
default:
- qemu_log_mask(LOG_UNIMP, "PSI: write at Ox%" PRIx32 "\n", offset);
+ qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
}
}
--
2.20.1
- [Qemu-devel] [PULL 22/62] ppc: externalize ppc_get_vcpu_by_pir(), (continued)
- [Qemu-devel] [PULL 22/62] ppc: externalize ppc_get_vcpu_by_pir(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 31/62] ppc/pnv: psi: add a PSIHB_REG macro, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 18/62] spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 35/62] target/ppc: introduce single vsrl_offset() function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 24/62] ppc/pnv: export the xive_router_notify() routine, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 21/62] ppc/xive: hardwire the Physical CAM line of the thread context, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 26/62] ppc/pnv: add a XIVE interrupt controller model for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 40/62] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 37/62] target/ppc: introduce avr_full_offset() function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 29/62] ppc/xive: activate HV support, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 30/62] ppc/pnv: fix logging primitives using Ox,
David Gibson <=
- [Qemu-devel] [PULL 34/62] target/ppc: introduce single fpr_offset() function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 44/62] ppc/pnv: add a PSI bridge model for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 33/62] spapr_iommu: Do not replay mappings from just created DMA window, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 43/62] ppc/pnv: add a PSI bridge class model, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 41/62] mac_oldworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 36/62] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 39/62] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 42/62] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 47/62] ppc/pnv: add a 'dt_isa_nodename' to the chip, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 49/62] ppc/pnv: add SerIRQ routing registers, David Gibson, 2019/03/12