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[Qemu-devel] [PULL 31/62] ppc/pnv: psi: add a PSIHB_REG macro
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 31/62] ppc/pnv: psi: add a PSIHB_REG macro |
Date: |
Tue, 12 Mar 2019 19:54:31 +1100 |
From: Cédric Le Goater <address@hidden>
This is a simple helper to translate XSCOM addresses to MMIO addresses
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_psi.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index c872be0b9c..a2f8d0dece 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -114,6 +114,8 @@
#define PSIHB_BAR_MASK 0x0003fffffff00000ull
#define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull
+#define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
+
static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
{
MemoryRegion *sysmem = get_system_memory();
@@ -392,13 +394,13 @@ static void pnv_psi_reg_write(PnvPsi *psi, uint32_t
offset, uint64_t val,
*/
static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
- return pnv_psi_reg_read(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, true);
+ return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
}
static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
- pnv_psi_reg_write(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, val, true);
+ pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
}
static const MemoryRegionOps psi_mmio_ops = {
--
2.20.1
- [Qemu-devel] [PULL 25/62] ppc/pnv: change the CPU machine_data presenter type to Object *, (continued)
- [Qemu-devel] [PULL 25/62] ppc/pnv: change the CPU machine_data presenter type to Object *, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 11/62] target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 20/62] PPC: E500: Add FSL I2C controller and integrate RTC with it, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 23/62] ppc/xive: export the TIMA memory accessors, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 19/62] target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 12/62] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 15/62] target/ppc: Refactor kvm_handle_debug, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 28/62] ppc/pnv: introduce a new pic_print_info() operation to the chip model, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 32/62] ppc/pnv: psi: add a reset handler, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 22/62] ppc: externalize ppc_get_vcpu_by_pir(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 31/62] ppc/pnv: psi: add a PSIHB_REG macro,
David Gibson <=
- [Qemu-devel] [PULL 18/62] spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 35/62] target/ppc: introduce single vsrl_offset() function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 24/62] ppc/pnv: export the xive_router_notify() routine, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 21/62] ppc/xive: hardwire the Physical CAM line of the thread context, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 26/62] ppc/pnv: add a XIVE interrupt controller model for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 40/62] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 37/62] target/ppc: introduce avr_full_offset() function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 29/62] ppc/xive: activate HV support, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 30/62] ppc/pnv: fix logging primitives using Ox, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 34/62] target/ppc: introduce single fpr_offset() function, David Gibson, 2019/03/12