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[Qemu-devel] [PULL 24/62] ppc/pnv: export the xive_router_notify() routi
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 24/62] ppc/pnv: export the xive_router_notify() routine |
Date: |
Tue, 12 Mar 2019 19:54:24 +1100 |
From: Cédric Le Goater <address@hidden>
The PowerNV machine with need to encode the block id in the source
interrupt number before forwarding the source event notification to
the Router.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/xive.c | 2 +-
include/hw/ppc/xive.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 3d7de864e9..7d7992c0ce 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1404,7 +1404,7 @@ static void xive_router_end_notify(XiveRouter *xrtr,
uint8_t end_blk,
/* TODO: Auto EOI. */
}
-static void xive_router_notify(XiveNotifier *xn, uint32_t lisn)
+void xive_router_notify(XiveNotifier *xn, uint32_t lisn)
{
XiveRouter *xrtr = XIVE_ROUTER(xn);
uint8_t eas_blk = XIVE_SRCNO_BLOCK(lisn);
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 7dd80e0f46..c4f27742ca 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -364,6 +364,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
uint32_t nvt_idx,
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
+void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
/*
* XIVE END ESBs
--
2.20.1
- [Qemu-devel] [PULL 23/62] ppc/xive: export the TIMA memory accessors, (continued)
- [Qemu-devel] [PULL 23/62] ppc/xive: export the TIMA memory accessors, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 19/62] target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 12/62] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 15/62] target/ppc: Refactor kvm_handle_debug, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 28/62] ppc/pnv: introduce a new pic_print_info() operation to the chip model, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 32/62] ppc/pnv: psi: add a reset handler, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 22/62] ppc: externalize ppc_get_vcpu_by_pir(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 31/62] ppc/pnv: psi: add a PSIHB_REG macro, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 18/62] spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 35/62] target/ppc: introduce single vsrl_offset() function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 24/62] ppc/pnv: export the xive_router_notify() routine,
David Gibson <=
- [Qemu-devel] [PULL 21/62] ppc/xive: hardwire the Physical CAM line of the thread context, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 26/62] ppc/pnv: add a XIVE interrupt controller model for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 40/62] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 37/62] target/ppc: introduce avr_full_offset() function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 29/62] ppc/xive: activate HV support, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 30/62] ppc/pnv: fix logging primitives using Ox, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 34/62] target/ppc: introduce single fpr_offset() function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 44/62] ppc/pnv: add a PSI bridge model for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 33/62] spapr_iommu: Do not replay mappings from just created DMA window, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 43/62] ppc/pnv: add a PSI bridge class model, David Gibson, 2019/03/12