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[Qemu-devel] [PATCH 5/9] tcg/i386: Support INDEX_op_extract2_{i32, i64}
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 5/9] tcg/i386: Support INDEX_op_extract2_{i32, i64} |
Date: |
Thu, 7 Mar 2019 06:41:22 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/i386/tcg-target.h | 4 ++--
tcg/i386/tcg-target.inc.c | 11 +++++++++++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 2c58eaa9ed..241bf19413 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -124,7 +124,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 1
-#define TCG_TARGET_HAS_extract2_i32 0
+#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@@ -163,7 +163,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0
-#define TCG_TARGET_HAS_extract2_i64 0
+#define TCG_TARGET_HAS_extract2_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index e0670e5098..1fa833840e 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -452,6 +452,7 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_SHUFPS (0xc6 | P_EXT)
#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
+#define OPC_SHRD_Ib (0xac | P_EXT)
#define OPC_TESTL (0x85)
#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
#define OPC_UD2 (0x0b | P_EXT)
@@ -2587,6 +2588,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
}
break;
+ OP_32_64(extract2):
+ /* Note that SHRD outputs to the r/m operand. */
+ tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
+ tcg_out8(s, args[3]);
+ break;
+
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
@@ -2845,6 +2852,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
+ static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
@@ -2970,6 +2978,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_ctpop_i32:
case INDEX_op_ctpop_i64:
return &r_r;
+ case INDEX_op_extract2_i32:
+ case INDEX_op_extract2_i64:
+ return &r_0_r;
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
--
2.17.2
- Re: [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64, (continued)
- [Qemu-devel] [PATCH 4/9] tcg: Use extract2 in tcg_gen_deposit_{i32, i64}, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64}, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH 5/9] tcg/i386: Support INDEX_op_extract2_{i32, i64},
Richard Henderson <=
- [Qemu-devel] [PATCH 6/9] tcg/arm: Support INDEX_op_extract2_i32, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH 7/9] tcg/aarch64: Support INDEX_op_extract2_{i32, i64}, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH 9/9] target/arm: Simplify BFXIL expansion, Richard Henderson, 2019/03/07
- [Qemu-devel] [PATCH 8/9] target/arm: Use extract2 for EXTR, Richard Henderson, 2019/03/07
- Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}, no-reply, 2019/03/07
- Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}, no-reply, 2019/03/07