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[Qemu-devel] [RFC v3 07/24] riscv: Add the tcg target registers
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [RFC v3 07/24] riscv: Add the tcg target registers |
Date: |
Sat, 8 Dec 2018 00:47:16 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 118 +++++++++++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
create mode 100644 tcg/riscv/tcg-target.inc.c
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
new file mode 100644
index 0000000000..6c969e3973
--- /dev/null
+++ b/tcg/riscv/tcg-target.inc.c
@@ -0,0 +1,118 @@
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2018 SiFive, Inc
+ * Copyright (c) 2008-2009 Arnaud Patard <address@hidden>
+ * Copyright (c) 2009 Aurelien Jarno <address@hidden>
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Based on i386/tcg-target.c and mips/tcg-target.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "tcg-pool.inc.c"
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "zero",
+ "ra",
+ "sp",
+ "gp",
+ "tp",
+ "t0",
+ "t1",
+ "t2",
+ "s0",
+ "s1",
+ "a0",
+ "a1",
+ "a2",
+ "a3",
+ "a4",
+ "a5",
+ "a6",
+ "a7",
+ "s2",
+ "s3",
+ "s4",
+ "s5",
+ "s6",
+ "s7",
+ "s8",
+ "s9",
+ "s10",
+ "s11",
+ "t3",
+ "t4",
+ "t5",
+ "t6"
+};
+#endif
+
+static const int tcg_target_reg_alloc_order[] = {
+ /* Call saved registers */
+ /* TCG_REG_S0 reservered for TCG_AREG0 */
+ TCG_REG_S1,
+ TCG_REG_S2,
+ TCG_REG_S3,
+ TCG_REG_S4,
+ TCG_REG_S5,
+ TCG_REG_S6,
+ TCG_REG_S7,
+ TCG_REG_S8,
+ TCG_REG_S9,
+ TCG_REG_S10,
+ TCG_REG_S11,
+
+ /* Call clobbered registers */
+ TCG_REG_T0,
+ TCG_REG_T1,
+ TCG_REG_T2,
+ TCG_REG_T3,
+ TCG_REG_T4,
+ TCG_REG_T5,
+ TCG_REG_T6,
+
+ /* Argument registers */
+ TCG_REG_A0,
+ TCG_REG_A1,
+ TCG_REG_A2,
+ TCG_REG_A3,
+ TCG_REG_A4,
+ TCG_REG_A5,
+ TCG_REG_A6,
+ TCG_REG_A7,
+};
+
+static const int tcg_target_call_iarg_regs[] = {
+ TCG_REG_A0,
+ TCG_REG_A1,
+ TCG_REG_A2,
+ TCG_REG_A3,
+ TCG_REG_A4,
+ TCG_REG_A5,
+ TCG_REG_A6,
+ TCG_REG_A7,
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_A0,
+ TCG_REG_A1,
+};
--
2.19.1
- [Qemu-devel] [RFC v3 00/24] Add RISC-V TCG backend support, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 01/24] elf.h: Add the RISCV ELF magic numbers, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 02/24] linux-user: Add host dependency for RISC-V 32-bit, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 03/24] linux-user: Add host dependency for RISC-V 64-bit, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 04/24] linux-user: riscv: Fix compile failure on riscv32 hosts, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 05/24] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 06/24] riscv: Add the tcg-target header file, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 07/24] riscv: Add the tcg target registers,
Alistair Francis <=
- [Qemu-devel] [RFC v3 08/24] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 09/24] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 10/24] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 11/24] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 12/24] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 13/24] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 14/24] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 15/24] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/07