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[Qemu-devel] [RFC v3 15/24] riscv: tcg-target: Add the add2 and sub2 ins
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [RFC v3 15/24] riscv: tcg-target: Add the add2 and sub2 instructions |
Date: |
Sat, 8 Dec 2018 00:48:33 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 55 ++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 04e81f811a..10bd007cd4 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -681,3 +681,58 @@ static bool tcg_out_sti(TCGContext *s, TCGType type,
TCGArg val,
}
return false;
}
+
+static void tcg_out_addsub2(TCGContext *s,
+ TCGReg rl, TCGReg rh,
+ TCGReg al, TCGReg ah,
+ TCGReg bl, TCGReg bh,
+ bool cbl, bool cbh, bool is_sub, bool is32bit)
+{
+ const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD;
+ const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI;
+ const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
+ TCGReg th = TCG_REG_TMP1;
+
+ /* If we have a negative constant such that negating it would
+ make the high part zero, we can (usually) eliminate one insn. */
+ if (cbl && cbh && bh == -1 && bl != 0) {
+ bl = -bl;
+ bh = 0;
+ is_sub = !is_sub;
+ }
+
+ /* By operating on the high part first, we get to use the final
+ carry operation to move back from the temporary. */
+ if (!cbh) {
+ tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
+ } else if (bh != 0 || ah == rl) {
+ tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
+ } else {
+ th = ah;
+ }
+
+ /* Note that tcg optimization should eliminate the bl == 0 case. */
+ if (is_sub) {
+ if (cbl) {
+ tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl);
+ tcg_out_opc_imm(s, opc_addi, rl, al, -bl);
+ } else {
+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl);
+ tcg_out_opc_reg(s, opc_sub, rl, al, bl);
+ }
+ tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
+ } else {
+ if (cbl) {
+ tcg_out_opc_imm(s, opc_addi, rl, al, bl);
+ tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
+ } else if (rl == al && rl == bl) {
+ tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
+ tcg_out_opc_reg(s, opc_addi, rl, al, bl);
+ } else {
+ tcg_out_opc_reg(s, opc_add, rl, al, bl);
+ tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
+ rl, (rl == bl ? al : bl));
+ }
+ tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
+ }
+}
--
2.19.1
- [Qemu-devel] [RFC v3 06/24] riscv: Add the tcg-target header file, (continued)
- [Qemu-devel] [RFC v3 06/24] riscv: Add the tcg-target header file, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 07/24] riscv: Add the tcg target registers, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 08/24] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 09/24] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 10/24] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 11/24] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 12/24] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 13/24] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 14/24] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 15/24] riscv: tcg-target: Add the add2 and sub2 instructions,
Alistair Francis <=
- [Qemu-devel] [RFC v3 16/24] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 17/24] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 18/24] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/07
- [Qemu-devel] [RFC v3 19/24] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/07