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[Qemu-devel] [PULL v1 31/38] target-microblaze: Simplify address computa
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 31/38] target-microblaze: Simplify address computation using tcg_gen_addi_i32() |
Date: |
Tue, 29 May 2018 12:50:04 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Simplify address computation using tcg_gen_addi_i32().
tcg_gen_addi_i32() already optimizes the case when the
immediate is zero.
No functional change.
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index bb6b5176c1..0d8ef77513 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -899,12 +899,7 @@ static inline void compute_ldst_addr(DisasContext *dc,
bool ea, TCGv t)
/* Immediate. */
t32 = tcg_temp_new_i32();
if (!extimm) {
- if (dc->imm == 0) {
- tcg_gen_mov_i32(t32, cpu_R[dc->ra]);
- } else {
- tcg_gen_movi_i32(t32, (int32_t)((int16_t)dc->imm));
- tcg_gen_add_i32(t32, cpu_R[dc->ra], t32);
- }
+ tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm);
} else {
tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
}
--
2.14.1
- [Qemu-devel] [PULL v1 21/38] target-microblaze: Setup for 64bit addressing, (continued)
- [Qemu-devel] [PULL v1 21/38] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 23/38] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 20/38] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 26/38] target-microblaze: mmu: Prepare for 64-bit addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 25/38] target-microblaze: mmu: Remove unused register state, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 27/38] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 28/38] target-microblaze: dec_msr: Plug a temp leak, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 30/38] target-microblaze: Allow address sizes between 32 and 64 bits, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 29/38] target-microblaze: Add support for extended access to TLBLO, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 31/38] target-microblaze: Simplify address computation using tcg_gen_addi_i32(),
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 32/38] target-microblaze: mmu: Cleanup debug log messages, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 33/38] target-microblaze: Use table based condition-codes conversion, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 36/38] target-microblaze: Use tcg_gen_movcond in eval_cond_jmp, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 34/38] target-microblaze: Remove argument b in eval_cc(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 35/38] target-microblaze: Convert env_btarget to i64, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 37/38] target-microblaze: cpu_mmu_index: Fixup indentation, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 38/38] target-microblaze: Consolidate MMU enabled checks, Edgar E. Iglesias, 2018/05/29
- Re: [Qemu-devel] [PULL v1 00/38] Xilinx queue, Peter Maydell, 2018/05/29