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[Qemu-devel] [PULL v1 33/38] target-microblaze: Use table based conditio
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 33/38] target-microblaze: Use table based condition-codes conversion |
Date: |
Tue, 29 May 2018 12:50:06 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Use a table based conversion to map condition-codes between
MicroBlaze ISA encoding and TCG.
No functional change.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 41 ++++++++++++++++++++---------------------
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 0d8ef77513..092e182c2f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1145,28 +1145,27 @@ static void dec_store(DisasContext *dc)
static inline void eval_cc(DisasContext *dc, unsigned int cc,
TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
+ static const int mb_to_tcg_cc[] = {
+ [CC_EQ] = TCG_COND_EQ,
+ [CC_NE] = TCG_COND_NE,
+ [CC_LT] = TCG_COND_LT,
+ [CC_LE] = TCG_COND_LE,
+ [CC_GE] = TCG_COND_GE,
+ [CC_GT] = TCG_COND_GT,
+ };
+
switch (cc) {
- case CC_EQ:
- tcg_gen_setcond_i32(TCG_COND_EQ, d, a, b);
- break;
- case CC_NE:
- tcg_gen_setcond_i32(TCG_COND_NE, d, a, b);
- break;
- case CC_LT:
- tcg_gen_setcond_i32(TCG_COND_LT, d, a, b);
- break;
- case CC_LE:
- tcg_gen_setcond_i32(TCG_COND_LE, d, a, b);
- break;
- case CC_GE:
- tcg_gen_setcond_i32(TCG_COND_GE, d, a, b);
- break;
- case CC_GT:
- tcg_gen_setcond_i32(TCG_COND_GT, d, a, b);
- break;
- default:
- cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc);
- break;
+ case CC_EQ:
+ case CC_NE:
+ case CC_LT:
+ case CC_LE:
+ case CC_GE:
+ case CC_GT:
+ tcg_gen_setcond_i32(mb_to_tcg_cc[cc], d, a, b);
+ break;
+ default:
+ cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc);
+ break;
}
}
--
2.14.1
- [Qemu-devel] [PULL v1 20/38] target-microblaze: Make special registers 64-bit, (continued)
- [Qemu-devel] [PULL v1 20/38] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 26/38] target-microblaze: mmu: Prepare for 64-bit addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 25/38] target-microblaze: mmu: Remove unused register state, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 27/38] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 28/38] target-microblaze: dec_msr: Plug a temp leak, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 30/38] target-microblaze: Allow address sizes between 32 and 64 bits, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 29/38] target-microblaze: Add support for extended access to TLBLO, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 31/38] target-microblaze: Simplify address computation using tcg_gen_addi_i32(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 32/38] target-microblaze: mmu: Cleanup debug log messages, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 33/38] target-microblaze: Use table based condition-codes conversion,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 36/38] target-microblaze: Use tcg_gen_movcond in eval_cond_jmp, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 34/38] target-microblaze: Remove argument b in eval_cc(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 35/38] target-microblaze: Convert env_btarget to i64, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 37/38] target-microblaze: cpu_mmu_index: Fixup indentation, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 38/38] target-microblaze: Consolidate MMU enabled checks, Edgar E. Iglesias, 2018/05/29
- Re: [Qemu-devel] [PULL v1 00/38] Xilinx queue, Peter Maydell, 2018/05/29