[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL v1 14/38] target-microblaze: Name special registers w
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 14/38] target-microblaze: Name special registers we support |
Date: |
Tue, 29 May 2018 12:49:47 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Name special registers we support.
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b36092b6fe..381f25348c 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -105,8 +105,8 @@ static const char *regnames[] =
static const char *special_regnames[] =
{
- "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
- "sr8", "sr9", "sr10", "sr11", "sr12", "sr13"
+ "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr",
+ "sr8", "sr9", "sr10", "rbtr", "sr12", "redr"
};
static inline void t_sync_flags(DisasContext *dc)
--
2.14.1
- [Qemu-devel] [PULL v1 04/38] target-microblaze: Fallback to our latest CPU version, (continued)
- [Qemu-devel] [PULL v1 04/38] target-microblaze: Fallback to our latest CPU version, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 02/38] target-microblaze: dec_store: Use bool instead of unsigned int, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 05/38] target-microblaze: Correct special register array sizes, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 06/38] target-microblaze: Correct the PVR array size, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 08/38] target-microblaze: Remove USE_MMU PVR checks, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 10/38] target-microblaze: Bypass MMU with MMU_NOMMU_IDX, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 11/38] target-microblaze: Make compute_ldst_addr always use a temp, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 12/38] target-microblaze: Remove pointer indirection for ld/st addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 07/38] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 14/38] target-microblaze: Name special registers we support,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 13/38] target-microblaze: Use TCGv for load/store addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 17/38] target-microblaze: dec_msr: Use bool and extract32, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 15/38] target-microblaze: Break out trap_userspace(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 19/38] target-microblaze: dec_msr: Fix MTS to FSR, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 16/38] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 18/38] target-microblaze: dec_msr: Reuse more code when reg-decoding, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 21/38] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 23/38] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 20/38] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/29