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[Qemu-devel] [PULL v1 12/38] target-microblaze: Remove pointer indirecti
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 12/38] target-microblaze: Remove pointer indirection for ld/st addresses |
Date: |
Tue, 29 May 2018 12:49:45 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 2a4546ec3d..ee17334959 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -848,7 +848,7 @@ static void dec_imm(DisasContext *dc)
dc->clear_imm = 0;
}
-static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t)
+static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t)
{
bool extimm = dc->tb_flags & IMM_FLAG;
/* Should be set to true if r1 is used by loadstores. */
@@ -863,10 +863,10 @@ static inline void compute_ldst_addr(DisasContext *dc,
TCGv_i32 *t)
if (!dc->type_b) {
/* If any of the regs is r0, set t to the value of the other reg. */
if (dc->ra == 0) {
- tcg_gen_mov_i32(*t, cpu_R[dc->rb]);
+ tcg_gen_mov_i32(t, cpu_R[dc->rb]);
return;
} else if (dc->rb == 0) {
- tcg_gen_mov_i32(*t, cpu_R[dc->ra]);
+ tcg_gen_mov_i32(t, cpu_R[dc->ra]);
return;
}
@@ -874,27 +874,27 @@ static inline void compute_ldst_addr(DisasContext *dc,
TCGv_i32 *t)
stackprot = true;
}
- tcg_gen_add_i32(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
+ tcg_gen_add_i32(t, cpu_R[dc->ra], cpu_R[dc->rb]);
if (stackprot) {
- gen_helper_stackprot(cpu_env, *t);
+ gen_helper_stackprot(cpu_env, t);
}
return;
}
/* Immediate. */
if (!extimm) {
if (dc->imm == 0) {
- tcg_gen_mov_i32(*t, cpu_R[dc->ra]);
+ tcg_gen_mov_i32(t, cpu_R[dc->ra]);
return;
}
- tcg_gen_movi_i32(*t, (int32_t)((int16_t)dc->imm));
- tcg_gen_add_i32(*t, cpu_R[dc->ra], *t);
+ tcg_gen_movi_i32(t, (int32_t)((int16_t)dc->imm));
+ tcg_gen_add_i32(t, cpu_R[dc->ra], t);
} else {
- tcg_gen_add_i32(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
+ tcg_gen_add_i32(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
}
if (stackprot) {
- gen_helper_stackprot(cpu_env, *t);
+ gen_helper_stackprot(cpu_env, t);
}
return;
}
@@ -929,7 +929,7 @@ static void dec_load(DisasContext *dc)
t_sync_flags(dc);
addr = tcg_temp_new_i32();
- compute_ldst_addr(dc, &addr);
+ compute_ldst_addr(dc, addr);
/*
* When doing reverse accesses we need to do two things.
@@ -1041,7 +1041,7 @@ static void dec_store(DisasContext *dc)
sync_jmpstate(dc);
/* SWX needs a temp_local. */
addr = ex ? tcg_temp_local_new_i32() : tcg_temp_new_i32();
- compute_ldst_addr(dc, &addr);
+ compute_ldst_addr(dc, addr);
if (ex) { /* swx */
TCGv_i32 tval;
--
2.14.1
- [Qemu-devel] [PULL v1 01/38] target-microblaze: dec_load: Use bool instead of unsigned int, (continued)
- [Qemu-devel] [PULL v1 01/38] target-microblaze: dec_load: Use bool instead of unsigned int, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 03/38] target-microblaze: compute_ldst_addr: Use bool instead of int, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 04/38] target-microblaze: Fallback to our latest CPU version, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 02/38] target-microblaze: dec_store: Use bool instead of unsigned int, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 05/38] target-microblaze: Correct special register array sizes, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 06/38] target-microblaze: Correct the PVR array size, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 08/38] target-microblaze: Remove USE_MMU PVR checks, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 10/38] target-microblaze: Bypass MMU with MMU_NOMMU_IDX, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 11/38] target-microblaze: Make compute_ldst_addr always use a temp, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 12/38] target-microblaze: Remove pointer indirection for ld/st addresses,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 07/38] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 14/38] target-microblaze: Name special registers we support, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 13/38] target-microblaze: Use TCGv for load/store addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 17/38] target-microblaze: dec_msr: Use bool and extract32, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 15/38] target-microblaze: Break out trap_userspace(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 19/38] target-microblaze: dec_msr: Fix MTS to FSR, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 16/38] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 18/38] target-microblaze: dec_msr: Reuse more code when reg-decoding, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 21/38] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 23/38] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/29