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Re: [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exception
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info |
Date: |
Thu, 26 Apr 2018 17:36:09 +0000 |
On Wed, Apr 25, 2018 at 4:59 PM Michael Clark <address@hidden> wrote:
> mtval/stval must be set on all exceptions but zero is
> a legal value if there is no exception specific info.
> Placing the instruction bytes for illegal instruction
> exceptions in mtval/stval is an optional feature and
> is currently not supported by QEMU RISC-V.
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> target/riscv/helper.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
> diff --git a/target/riscv/helper.c b/target/riscv/helper.c
> index 459fc97..3b57e13 100644
> --- a/target/riscv/helper.c
> +++ b/target/riscv/helper.c
> @@ -492,6 +492,10 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> ": badaddr 0x" TARGET_FMT_lx, env->mhartid,
env->badaddr);
> }
> env->sbadaddr = env->badaddr;
> + } else {
> + /* otherwise we must clear sbadaddr/stval
> + * todo: support populating stval on illegal instructions */
> + env->sbadaddr = 0;
> }
> target_ulong s = env->mstatus;
> @@ -513,6 +517,10 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> ": badaddr 0x" TARGET_FMT_lx, env->mhartid,
env->badaddr);
> }
> env->mbadaddr = env->badaddr;
> + } else {
> + /* otherwise we must clear mbadaddr/mtval
> + * todo: support populating mtval on illegal instructions */
> + env->mbadaddr = 0;
> }
> target_ulong s = env->mstatus;
> --
> 2.7.0
- Re: [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code, (continued)
- [Qemu-devel] [PATCH v8 13/35] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 14/35] RISC-V: Update E order and I extension order, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info,
Alistair Francis <=
- [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/04/25