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[Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -i
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto |
Date: |
Thu, 26 Apr 2018 11:45:24 +1200 |
Previously the mycycle/minstret CSRs and rdcycle/rdinstret
psuedo instructions would return the time as a proxy for an
increasing instruction counter in the absence of having a
precise instruction count. If QEMU is invoked with -icount,
the mcycle/minstret CSRs and rdcycle/rdinstret psuedo
instructions will return the instruction count.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/op_helper.c | 24 ++++++++++++++++++++----
target/riscv/translate.c | 2 ++
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 2daf07c..7d3f1ee 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -433,25 +433,41 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
case CSR_INSTRET:
case CSR_CYCLE:
if (ctr_ok) {
- return cpu_get_host_ticks();
+ if (use_icount) {
+ return cpu_get_icount();
+ } else {
+ return cpu_get_host_ticks();
+ }
}
break;
#if defined(TARGET_RISCV32)
case CSR_INSTRETH:
case CSR_CYCLEH:
if (ctr_ok) {
- return cpu_get_host_ticks() >> 32;
+ if (use_icount) {
+ return cpu_get_icount() >> 32;
+ } else {
+ return cpu_get_host_ticks() >> 32;
+ }
}
break;
#endif
#ifndef CONFIG_USER_ONLY
case CSR_MINSTRET:
case CSR_MCYCLE:
- return cpu_get_host_ticks();
+ if (use_icount) {
+ return cpu_get_icount();
+ } else {
+ return cpu_get_host_ticks();
+ }
case CSR_MINSTRETH:
case CSR_MCYCLEH:
#if defined(TARGET_RISCV32)
- return cpu_get_host_ticks() >> 32;
+ if (use_icount) {
+ return cpu_get_icount() >> 32;
+ } else {
+ return cpu_get_host_ticks() >> 32;
+ }
#endif
break;
case CSR_MUCOUNTEREN:
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c3a029a..c0e6a04 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1390,6 +1390,7 @@ static void gen_system(CPURISCVState *env, DisasContext
*ctx, uint32_t opc,
break;
default:
tcg_gen_movi_tl(imm_rs1, rs1);
+ gen_io_start();
switch (opc) {
case OPC_RISC_CSRRW:
gen_helper_csrrw(dest, cpu_env, source1, csr_store);
@@ -1413,6 +1414,7 @@ static void gen_system(CPURISCVState *env, DisasContext
*ctx, uint32_t opc,
gen_exception_illegal(ctx);
return;
}
+ gen_io_end();
gen_set_gpr(rd, dest);
/* end tb since we may be changing priv modes, to get mmu_index right
*/
tcg_gen_movi_tl(cpu_pc, ctx->next_pc);
--
2.7.0
- [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case, (continued)
- [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto,
Michael Clark <=
- [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/04/25