[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vector
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps |
Date: |
Thu, 26 Apr 2018 17:27:51 +0000 |
On Wed, Apr 25, 2018 at 5:08 PM Michael Clark <address@hidden> wrote:
> Vectored traps for asynchrounous interrupts are optional.
> The mtvec/stvec mode field is WARL and hence does not trap
> if an illegal value is written. Illegal values are ignored.
> Later we can add RISCV_FEATURE_VECTORED_TRAPS however
> until then the correct behavior for WARL (Write Any, Read
> Legal) fields is to drop writes to unsupported bits.
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> target/riscv/op_helper.c | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 101dac1..828f20c 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -276,11 +276,10 @@ void csr_write_helper(CPURISCVState *env,
target_ulong val_to_write,
> env->sepc = val_to_write;
> break;
> case CSR_STVEC:
> - if (val_to_write & 1) {
> - qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not
supported");
Should the unimplemented log be removed?
Alistair
> - goto do_illegal;
> + /* we do not support vectored traps for asynchrounous interrupts
*/
> + if ((val_to_write & 3) == 0) {
> + env->stvec = val_to_write >> 2 << 2;
> }
> - env->stvec = val_to_write >> 2 << 2;
> break;
> case CSR_SCOUNTEREN:
> env->scounteren = val_to_write;
> @@ -298,11 +297,10 @@ void csr_write_helper(CPURISCVState *env,
target_ulong val_to_write,
> env->mepc = val_to_write;
> break;
> case CSR_MTVEC:
> - if (val_to_write & 1) {
> - qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not
supported");
> - goto do_illegal;
> + /* we do not support vectored traps for asynchrounous interrupts
*/
> + if ((val_to_write & 3) == 0) {
> + env->mtvec = val_to_write >> 2 << 2;
> }
> - env->mtvec = val_to_write >> 2 << 2;
> break;
> case CSR_MCOUNTEREN:
> env->mcounteren = val_to_write;
> --
> 2.7.0
- Re: [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c, (continued)
- [Qemu-devel] [PATCH v8 12/35] RISC-V: Update address bits to support sv39 and sv48, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 13/35] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 14/35] RISC-V: Update E order and I extension order, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps,
Alistair Francis <=
- [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps, Michael Clark, 2018/04/25