Re: [Qemu-devel] Questions regarding emulated UART in VersatilePB board

[Ramy Sameh]

Thank you very much Peter.

I will check the documentation for VersatilePB and ARM926EJ-S for more
understanding of interrupts handling.



On Tue, Sep 5, 2017 at 8:06 PM, Peter Maydell <address@hidden>
wrote:

> On 5 September 2017 at 18:56, Ramy Sameh <address@hidden> wrote:
> > Are there any documentation or source of information, that can describe
> how
> > interrupts are implemented, and how to use them (where is the vector
> table
> > to put the ISR ... etc) ?
>
> The source code is it.
>
> Note that the pl011 is only a UART. It is used in a variety
> of different boards, which have different interrupt controllers,
> and with different CPUs. Things like ISR vector tables are
> generally part of the CPU or interrupt controller emulation.
>
> The pl011's part of this is simply to raise and lower its outbound IRQ line
> when the conditions are right -- this happens by calling qemu_set_irq()
> in pl011_update(). This corresponds to the hardware's UARTINTR line.
> In QEMU that IRQ line is connected up to an emulated interrupt controller
> which in turn is connected to an emulated CPU, just as in hardware
> the pl011 UARTINTR line is connected to a hardware interrupt controller
> and thus to a CPU.
>
> For information on how guest code should use a UART, how it should
> set up interrupts and so on, you should consult the documentation
> on how the hardware behaves.
>
> > In addition, any source of info that describes the code workflow when
> > reading or writing to the uart would be very helpful.
> > (because I put printfs in the functions to understand the workflow, but
> the
> > order of these printfs made me very confused).
> >
> > Regarding the registers, I have checked pl011_read and pl011_write, and
> > found them, thanks for that.
> > But I couldn't find the register "UARTICR" (Interrupt clear register)
> > I think this might be related to my lack of understanding of how
> interrupts
> > are implemented in emulated pl011.
>
> UARTICR is a write-only register, so it is handled only in
> pl011_write():
>
>     case 17: /* UARTICR */
>         s->int_level &= ~value;
>         pl011_update(s);
>         break;
>
> (It's write-1-to-clear, hence the &= ~.)
>
> > Regarding the ID registers, whose values are hard-wired in the board, and
> > there was no need to implement modifiable states for them.
> > Do you mean Peripheral identification registers, UARTPeriphID0-3 and
> > PrimeCell identification registers, UARTPCellID0-3 ?
>
> Yes. (See the pl011_id_arm[] array which has the values.)
>
> thanks
> -- PMM
>



-- 
Best Regards,
Ramy Sameh
Embedded Software Engineer
+2-010-172-777-14