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[Qemu-devel] [PULL 35/36] target/arm: Fix aa64 ldp register writeback
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 35/36] target/arm: Fix aa64 ldp register writeback |
Date: |
Mon, 4 Sep 2017 13:26:06 +0100 |
From: Richard Henderson <address@hidden>
For "ldp x0, x1, [x0]", if the second load is on a second page and
the second page is unmapped, the exception would be raised with x0
already modified. This means the instruction couldn't be restarted.
Cc: address@hidden
Cc: address@hidden
Reported-by: Andrew <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Fixes: https://bugs.launchpad.net/qemu/+bug/1713066
Signed-off-by: Richard Henderson <address@hidden>
[PMM: tweaked comment format]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25..cb44632 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2217,29 +2217,34 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
} else {
do_fp_st(s, rt, tcg_addr, size);
}
- } else {
- TCGv_i64 tcg_rt = cpu_reg(s, rt);
- if (is_load) {
- do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,
- false, 0, false, false);
- } else {
- do_gpr_st(s, tcg_rt, tcg_addr, size,
- false, 0, false, false);
- }
- }
- tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
- if (is_vector) {
+ tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
if (is_load) {
do_fp_ld(s, rt2, tcg_addr, size);
} else {
do_fp_st(s, rt2, tcg_addr, size);
}
} else {
+ TCGv_i64 tcg_rt = cpu_reg(s, rt);
TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
+
if (is_load) {
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ /* Do not modify tcg_rt before recognizing any exception
+ * from the second load.
+ */
+ do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false,
+ false, 0, false, false);
+ tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false,
false, 0, false, false);
+
+ tcg_gen_mov_i64(tcg_rt, tmp);
+ tcg_temp_free_i64(tmp);
} else {
+ do_gpr_st(s, tcg_rt, tcg_addr, size,
+ false, 0, false, false);
+ tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
do_gpr_st(s, tcg_rt2, tcg_addr, size,
false, 0, false, false);
}
--
2.7.4
- [Qemu-devel] [PULL 25/36] memory.h: Move MemTxResult type to memattrs.h, (continued)
- [Qemu-devel] [PULL 25/36] memory.h: Move MemTxResult type to memattrs.h, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 20/36] target/arm/kvm: pmu: split init and set-irq stages, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 23/36] watchdog: wdt_aspeed: Add support for the reset width register, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 26/36] cpu: Define new cpu_transaction_failed() hook, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 32/36] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 34/36] hw/arm/digic: Mark device with user_creatable = false, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 27/36] cputlb: Support generating CPU exceptions on memory transaction failures, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 31/36] target/arm: Allow deliver_fault() caller to specify EA bit, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 33/36] hw/arm/aspeed_soc: Mark devices as user_creatable = false, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 29/36] hw/arm: Set ignore_memory_transaction_failures for most ARM boards, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 35/36] target/arm: Fix aa64 ldp register writeback,
Peter Maydell <=
- [Qemu-devel] [PULL 36/36] arm_gicv3_kvm: Fix compile warning, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 28/36] boards.h: Define new flag ignore_memory_transaction_failures, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 30/36] target/arm: Factor out fault delivery code, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 00/36] target-arm queue, Peter Maydell, 2017/09/04