[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 25/36] memory.h: Move MemTxResult type to memattrs.h
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 25/36] memory.h: Move MemTxResult type to memattrs.h |
Date: |
Mon, 4 Sep 2017 13:25:56 +0100 |
Move the MemTxResult type to memattrs.h. We're going to want to
use it in cpu/qom.h, which doesn't want to include all of
memory.h. In practice MemTxResult and MemTxAttrs are pretty
closely linked since both are used for the new-style
read_with_attrs and write_with_attrs callbacks, so memattrs.h
is a reasonable home for this rather than creating a whole
new header file for it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
include/exec/memattrs.h | 10 ++++++++++
include/exec/memory.h | 10 ----------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index e601061..d4a1642 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -46,4 +46,14 @@ typedef struct MemTxAttrs {
*/
#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 })
+/* New-style MMIO accessors can indicate that the transaction failed.
+ * A zero (MEMTX_OK) response means success; anything else is a failure
+ * of some kind. The memory subsystem will bitwise-OR together results
+ * if it is synthesizing an operation from multiple smaller accesses.
+ */
+#define MEMTX_OK 0
+#define MEMTX_ERROR (1U << 0) /* device returned an error */
+#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
+typedef uint32_t MemTxResult;
+
#endif
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 400dd44..1dcd312 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -112,16 +112,6 @@ static inline void iommu_notifier_init(IOMMUNotifier *n,
IOMMUNotify fn,
n->end = end;
}
-/* New-style MMIO accessors can indicate that the transaction failed.
- * A zero (MEMTX_OK) response means success; anything else is a failure
- * of some kind. The memory subsystem will bitwise-OR together results
- * if it is synthesizing an operation from multiple smaller accesses.
- */
-#define MEMTX_OK 0
-#define MEMTX_ERROR (1U << 0) /* device returned an error */
-#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
-typedef uint32_t MemTxResult;
-
/*
* Memory region callbacks
*/
--
2.7.4
- [Qemu-devel] [PULL 13/36] target/arm: Create and use new function arm_v7m_is_handler_mode(), (continued)
- [Qemu-devel] [PULL 13/36] target/arm: Create and use new function arm_v7m_is_handler_mode(), Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 18/36] hw/arm: use defined type name instead of hard-coded string, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 15/36] nvic: Implement "user accesses BusFault" SCS region behaviour, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 14/36] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 16/36] loader: Handle ELF files with overlapping zero-initialized data, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 19/36] hw/arm/virt: add pmu interrupt state, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 22/36] target/arm/kvm: pmu: improve error handling, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 17/36] loader: Ignore zero-sized ELF segments, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 21/36] hw/arm/virt: allow pmu instantiation with userspace irqchip, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 24/36] aspeed_soc: Propagate silicon-rev to watchdog, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 25/36] memory.h: Move MemTxResult type to memattrs.h,
Peter Maydell <=
- [Qemu-devel] [PULL 20/36] target/arm/kvm: pmu: split init and set-irq stages, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 23/36] watchdog: wdt_aspeed: Add support for the reset width register, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 26/36] cpu: Define new cpu_transaction_failed() hook, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 32/36] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 34/36] hw/arm/digic: Mark device with user_creatable = false, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 27/36] cputlb: Support generating CPU exceptions on memory transaction failures, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 31/36] target/arm: Allow deliver_fault() caller to specify EA bit, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 33/36] hw/arm/aspeed_soc: Mark devices as user_creatable = false, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 29/36] hw/arm: Set ignore_memory_transaction_failures for most ARM boards, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 35/36] target/arm: Fix aa64 ldp register writeback, Peter Maydell, 2017/09/04