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From: | Richard Henderson |
Subject: | Re: [Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target stubs inside target-riscv/ |
Date: | Mon, 26 Sep 2016 14:50:58 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 |
On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
+typedef struct CPURISCVState CPURISCVState; +struct CPURISCVState { + target_ulong gpr[32]; + uint64_t fpr[32]; /* assume both F and D extensions */ + target_ulong PC; + target_ulong load_res; + + target_ulong csr[4096]; /* RISCV CSR registers */
This is 16k for 32-bit, and 32k for 64-bit, most of which is unused.I think it would be better to add only the CSRs that you actually need for the implementation.
r~
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