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Re: [Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floati
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions |
Date: |
Mon, 26 Sep 2016 14:35:45 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 |
On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
+uint64_t helper_fsgnj_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+{
+ frs1 = (frs1 & ~(uint32_t)INT32_MIN) | (frs2 & (uint32_t)INT32_MIN);
+ return frs1;
+}
+
+uint64_t helper_fsgnjn_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+{
+ frs1 = (frs1 & ~(uint32_t)INT32_MIN) | ((~frs2) & (uint32_t)INT32_MIN);
+ return frs1;
+}
+
+uint64_t helper_fsgnjx_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+{
+ frs1 = frs1 ^ (frs2 & (uint32_t)INT32_MIN);
+ return frs1;
+}
These are simple enough to implement inline.
+
+uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+{
+ frs1 = float32_is_any_nan(frs2) ||
+ float32_lt_quiet(frs1, frs2, &env->fp_status) ? frs1 : frs2;
+ set_fp_exceptions();
+ return frs1;
+}
float32_minnum.
+
+uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
+{
+ frs1 = float32_is_any_nan(frs2) ||
+ float32_le_quiet(frs2, frs1, &env->fp_status) ? frs1 : frs2;
+ set_fp_exceptions();
+ return frs1;
+}
float32_maxnum.
+target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t frs1, uint64_t rm)
+{
+ set_float_rounding_mode(RM, &env->fp_status);
+ frs1 = (int64_t)((int32_t)float32_to_int32(frs1, &env->fp_status));
You do not need either of these casts.
+target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t frs1, uint64_t rm)
+{
+ set_float_rounding_mode(RM, &env->fp_status);
+ frs1 = (int64_t)((int32_t)float32_to_uint32(frs1, &env->fp_status));
You do not need the cast to int64_t. Also, remove the extra parenthesis.
+union ui32_f32 { uint32_t ui; uint32_t f; };
What's the point of this?
+
+uint_fast16_t float32_classify(uint32_t a, float_status *status)
No need for uint_fast16_t. Just use uint32_t.
+{
+ union ui32_f32 uA;
+ uint_fast32_t uiA;
+
+ uA.f = a;
+ uiA = uA.ui;
+
+ uint_fast16_t infOrNaN = expF32UI(uiA) == 0xFF;
float32_is_infinity or float32_is_any_nan.
+ uint_fast16_t subnormalOrZero = expF32UI(uiA) == 0;
float32_is_zero_or_denormal
+ bool sign = signF32UI(uiA);
float32_is_neg.
r~
- Re: [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions, (continued)
- [Qemu-devel] [PATCH 13/18] target-riscv: Add CSR read/write helpers, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 05/18] target-riscv: Add Arithmetic instructions, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 18/18] target-riscv: Add generic test board, activate target, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 11/18] target-riscv: Add Double Precision Floating-Point Instructions, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions, Sagar Karandikar, 2016/09/26
- Re: [Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions,
Richard Henderson <=
- [Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target stubs inside target-riscv/, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 17/18] target-riscv: Add support for Host-Target Interface (HTIF) Devices, Sagar Karandikar, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Paolo Bonzini, 2016/09/26