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Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation s
From: |
Paolo Bonzini |
Subject: |
Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G) |
Date: |
Mon, 26 Sep 2016 18:37:04 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 |
On 26/09/2016 18:35, Andreas Färber wrote:
> Am 26.09.2016 um 18:24 schrieb Paolo Bonzini:
>> On 26/09/2016 18:20, Andreas Färber wrote:
>>> Am 26.09.2016 um 18:17 schrieb Richard Henderson:
>>>> On 09/26/2016 05:20 AM, Paolo Bonzini wrote:
>>>>> On 26/09/2016 12:56, Sagar Karandikar wrote:
>>>>>> -cpu-qom.h merged into cpu.h
>>>>>
>>>>> Please follow the model of other targets. RISCVCPUClass and the
>>>>> RISCVCPU typedef should be in cpu-qom.h.
>
> After discussion with Paolo, the key word here is typedef. It doesn't
> make sense to have the struct RISCVCPU in cpu-qom.h (the old approach)
> but it makes perfect sense to have struct RISCVCPUClass and typedef
> RISCVCPU in a separate cpu-qom.h.
Thanks Andreas, and sorry Sagar for the back-and-forth!
Paolo
- [Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode, (continued)
- [Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target stubs inside target-riscv/, Sagar Karandikar, 2016/09/26
- [Qemu-devel] [PATCH 17/18] target-riscv: Add support for Host-Target Interface (HTIF) Devices, Sagar Karandikar, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Paolo Bonzini, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Richard Henderson, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Andreas Färber, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Paolo Bonzini, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G), Andreas Färber, 2016/09/26
- Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G),
Paolo Bonzini <=