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[Qemu-devel] [PATCH RFC v1 25/29] target-arc: TRAP, SWI
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH RFC v1 25/29] target-arc: TRAP, SWI |
Date: |
Fri, 9 Sep 2016 01:32:06 +0300 |
Signed-off-by: Michael Rolnik <address@hidden>
---
target-arc/translate-inst.c | 105 ++++++++++++++++++++++++++++++++++++++++++++
target-arc/translate-inst.h | 4 ++
2 files changed, 109 insertions(+)
diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index 4c4318f..87a00ca 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -2698,3 +2698,108 @@ int arc_gen_UNIMP(DisasCtxt *ctx)
return BS_EXCP;
}
+
+/*
+ TRAP
+*/
+int arc_gen_TRAP(DisasCtxt *ctx, TCGv src1)
+{
+ if (arc_feature(ctx->env, ARC_FEATURE_ARC700)) {
+ tcg_gen_mov_tl(cpu_er_Lf, cpu_Lf);
+ tcg_gen_mov_tl(cpu_er_Zf, cpu_Zf);
+ tcg_gen_mov_tl(cpu_er_Nf, cpu_Nf);
+ tcg_gen_mov_tl(cpu_er_Cf, cpu_Cf);
+ tcg_gen_mov_tl(cpu_er_Vf, cpu_Vf);
+ tcg_gen_mov_tl(cpu_er_Uf, cpu_Uf);
+
+ tcg_gen_mov_tl(cpu_er_DEf, cpu_DEf);
+ tcg_gen_mov_tl(cpu_er_AEf, cpu_AEf);
+ tcg_gen_mov_tl(cpu_er_A2f, cpu_A2f);
+ tcg_gen_mov_tl(cpu_er_A1f, cpu_A1f);
+ tcg_gen_mov_tl(cpu_er_E2f, cpu_E2f);
+ tcg_gen_mov_tl(cpu_er_E1f, cpu_E1f);
+ tcg_gen_mov_tl(cpu_er_Hf, cpu_Hf);
+
+ tcg_gen_movi_tl(cpu_E1f, 0);
+ tcg_gen_movi_tl(cpu_E2f, 0);
+ tcg_gen_movi_tl(cpu_AEf, 1);
+ tcg_gen_movi_tl(cpu_Uf, 0);
+
+ tcg_gen_movi_tl(cpu_eret, ctx->npc);
+ tcg_gen_movi_tl(cpu_efa, ctx->cpc);
+ tcg_gen_andi_tl(cpu_ecr, src1, 0x000000ff);
+ tcg_gen_ori_tl(cpu_ecr, cpu_ecr, 0x00250000);
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_erbta, cpu_DEf, ctx->zero,
+ cpu_bta, cpu_erbta);
+
+ tcg_gen_andi_tl(cpu_pc, cpu_intvec, 0xffffffc0);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, 0x128);
+ } else {
+ arc_gen_UNIMP(ctx);
+ }
+
+ return BS_EXCP;
+}
+
+/*
+ SWI
+*/
+int arc_gen_SWI(DisasCtxt *ctx)
+{
+ if (arc_feature(ctx->env, ARC_FEATURE_ARC700)) {
+ tcg_gen_mov_tl(cpu_er_Lf, cpu_Lf);
+ tcg_gen_mov_tl(cpu_er_Zf, cpu_Zf);
+ tcg_gen_mov_tl(cpu_er_Nf, cpu_Nf);
+ tcg_gen_mov_tl(cpu_er_Cf, cpu_Cf);
+ tcg_gen_mov_tl(cpu_er_Vf, cpu_Vf);
+ tcg_gen_mov_tl(cpu_er_Uf, cpu_Uf);
+
+ tcg_gen_mov_tl(cpu_er_DEf, cpu_DEf);
+ tcg_gen_mov_tl(cpu_er_AEf, cpu_AEf);
+ tcg_gen_mov_tl(cpu_er_A2f, cpu_A2f);
+ tcg_gen_mov_tl(cpu_er_A1f, cpu_A1f);
+ tcg_gen_mov_tl(cpu_er_E2f, cpu_E2f);
+ tcg_gen_mov_tl(cpu_er_E1f, cpu_E1f);
+ tcg_gen_mov_tl(cpu_er_Hf, cpu_Hf);
+
+ tcg_gen_movi_tl(cpu_E1f, 0);
+ tcg_gen_movi_tl(cpu_E2f, 0);
+ tcg_gen_movi_tl(cpu_AEf, 1);
+ tcg_gen_movi_tl(cpu_Uf, 0);
+
+ tcg_gen_movi_tl(cpu_eret, ctx->npc);
+ tcg_gen_movi_tl(cpu_efa, ctx->cpc);
+ tcg_gen_movi_tl(cpu_ecr, 0x00250000);
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_erbta, cpu_DEf, ctx->zero,
+ cpu_bta, cpu_erbta);
+
+ tcg_gen_andi_tl(cpu_pc, cpu_intvec, 0xffffffc0);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, 0x128);
+ } else {
+ tcg_gen_movi_tl(cpu_ilink2, ctx->npc);
+
+ tcg_gen_mov_tl(cpu_l2_Lf, cpu_Lf);
+ tcg_gen_mov_tl(cpu_l2_Zf, cpu_Zf);
+ tcg_gen_mov_tl(cpu_l2_Nf, cpu_Nf);
+ tcg_gen_mov_tl(cpu_l2_Cf, cpu_Cf);
+ tcg_gen_mov_tl(cpu_l2_Vf, cpu_Vf);
+ tcg_gen_mov_tl(cpu_l2_Uf, cpu_Uf);
+
+ tcg_gen_mov_tl(cpu_l2_DEf, cpu_DEf);
+ tcg_gen_mov_tl(cpu_l2_AEf, cpu_AEf);
+ tcg_gen_mov_tl(cpu_l2_A2f, cpu_A2f);
+ tcg_gen_mov_tl(cpu_l2_A1f, cpu_A1f);
+ tcg_gen_mov_tl(cpu_l2_E2f, cpu_E2f);
+ tcg_gen_mov_tl(cpu_l2_E1f, cpu_E1f);
+ tcg_gen_mov_tl(cpu_l2_Hf, cpu_Hf);
+
+ tcg_gen_movi_tl(cpu_E1f, 0);
+ tcg_gen_movi_tl(cpu_E2f, 0);
+
+ tcg_gen_andi_tl(cpu_pc, cpu_intvec, 0xffffffc0);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, 0x10);
+ }
+
+ return BS_EXCP;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index 9f88d03..f7f988b 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -165,3 +165,7 @@ int arc_gen_FLAG(DisasCtxt *c, TCGv src1);
int arc_gen_NOP(DisasCtxt *c);
int arc_gen_UNIMP(DisasCtxt *c);
+
+int arc_gen_SWI(DisasCtxt *c);
+int arc_gen_TRAP(DisasCtxt *c, TCGv src1);
+
--
2.4.9 (Apple Git-60)
- [Qemu-devel] [PATCH RFC v1 18/29] target-arc: J, JL, (continued)
- [Qemu-devel] [PATCH RFC v1 18/29] target-arc: J, JL, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 17/29] target-arc: B, BL, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 19/29] target-arc: LR, SR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 22/29] target-arc: ASLS, ASRS, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 20/29] target-arc: ADDS, ADDSDW, SUBS, SUBSDW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 21/29] target-arc: ABSS, ABSSW, NEGS, NEGSW, RND16, SAT16, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 23/29] target-arc: FLAG, BRK, SLEEP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 25/29] target-arc: TRAP, SWI,
Michael Rolnik <=
- [Qemu-devel] [PATCH RFC v1 24/29] target-arc: NOP, UNIMP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 26/29] target-arc: RTIE, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 27/29] target-arc: LP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 29/29] target-arc: sample board, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 28/29] target-arc: decode, Michael Rolnik, 2016/09/08
- Re: [Qemu-devel] [PATCH RFC v1 00/29] ARC cores, Alexey Brodkin, 2016/09/16