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[Qemu-devel] [PATCH RFC v1 22/29] target-arc: ASLS, ASRS
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH RFC v1 22/29] target-arc: ASLS, ASRS |
Date: |
Fri, 9 Sep 2016 01:32:03 +0300 |
Signed-off-by: Michael Rolnik <address@hidden>
---
target-arc/translate-inst.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
target-arc/translate-inst.h | 3 +++
2 files changed, 60 insertions(+)
diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index 2a62f30..524b213 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -2560,3 +2560,60 @@ int arc_gen_SAT16(DisasCtxt *ctx, TCGv dest, TCGv src1)
return BS_NONE;
}
+/*
+ ASLS
+*/
+int arc_gen_ASLS(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+ /* TODO */
+
+ return BS_NONE;
+}
+
+
+/*
+ ASRS
+*/
+int arc_gen_ASRS(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+ /* TODO: check */
+ TCGv rslt = dest;
+ TCGv shft = tcg_temp_new_i32();
+ TCGLabel *label_pos = gen_new_label();
+ TCGLabel *label_done = gen_new_label();
+
+ if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_brcond_tl(TCG_COND_LEU, src2, ctx->smax32, label_pos);
+
+ /* negative */
+ tcg_gen_movcond_tl(TCG_COND_GT, shft, src2, ctx->smin5, src2, ctx->smin5);
+ tcg_gen_neg_tl(shft, shft);
+ tcg_gen_shl_tl(rslt, src1, shft);
+
+ tcg_gen_br(label_done);
+
+gen_set_label(label_pos);
+ /* positive */
+ tcg_gen_movcond_tl(TCG_COND_LT, shft, src2, ctx->smax5, src2, ctx->smax5);
+ tcg_gen_sar_tl(rslt, src1, shft);
+
+gen_set_label(label_done);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_sari_tl(cpu_Nf, rslt, 31);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ tcg_temp_free_i32(shft);
+
+ return BS_NONE;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index c84d989..e2b76d4 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -156,3 +156,6 @@ int arc_gen_RND16(DisasCtxt *c, TCGv dest, TCGv src1);
int arc_gen_NEGS(DisasCtxt *c, TCGv dest, TCGv src1);
int arc_gen_NEGSW(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_ASLS(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_ASRS(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2);
+
--
2.4.9 (Apple Git-60)
- [Qemu-devel] [PATCH RFC v1 12/29] target-arc: RLC, RRC, (continued)
- [Qemu-devel] [PATCH RFC v1 12/29] target-arc: RLC, RRC, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 14/29] target-arc: MPY, MPYH, MPYHU, MPYU, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 16/29] target-arc: BBIT0, BBIT1, BR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 18/29] target-arc: J, JL, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 17/29] target-arc: B, BL, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 19/29] target-arc: LR, SR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 22/29] target-arc: ASLS, ASRS,
Michael Rolnik <=
- [Qemu-devel] [PATCH RFC v1 20/29] target-arc: ADDS, ADDSDW, SUBS, SUBSDW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 21/29] target-arc: ABSS, ABSSW, NEGS, NEGSW, RND16, SAT16, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 23/29] target-arc: FLAG, BRK, SLEEP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 25/29] target-arc: TRAP, SWI, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 24/29] target-arc: NOP, UNIMP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 26/29] target-arc: RTIE, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 27/29] target-arc: LP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 29/29] target-arc: sample board, Michael Rolnik, 2016/09/08