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[Qemu-devel] [PATCH RFC v1 09/29] target-arc: NEG, ABS, NOT
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH RFC v1 09/29] target-arc: NEG, ABS, NOT |
Date: |
Fri, 9 Sep 2016 01:31:50 +0300 |
Signed-off-by: Michael Rolnik <address@hidden>
---
target-arc/translate-inst.c | 68 +++++++++++++++++++++++++++++++++++++++++++++
target-arc/translate-inst.h | 4 +++
2 files changed, 72 insertions(+)
diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index 4d756a9..7f7e951 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -1079,3 +1079,71 @@ int arc_gen_SWAP(DisasCtxt *ctx, TCGv dest, TCGv src1)
return BS_NONE;
}
+/*
+ ABS
+*/
+int arc_gen_ABS(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ TCGv rslt = dest;
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ if (TCGV_EQUAL(dest, src1)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_neg_i32(t0, src1);
+ tcg_gen_movcond_tl(TCG_COND_GEU, rslt, src1, ctx->msb32, src1, t0);
+
+ tcg_temp_free_i32(t0);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_shri_tl(cpu_Cf, src1, 31);
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Nf, src1, ctx->msb32);
+ tcg_gen_mov_tl(cpu_Vf, cpu_Nf);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ return BS_NONE;
+}
+
+/*
+ NEG
+*/
+int arc_gen_NEG(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ arc_gen_SUB(ctx, dest, ctx->zero, src1);
+
+ return BS_NONE;
+}
+
+/*
+ NOT
+*/
+int arc_gen_NOT(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ TCGv rslt = dest;
+
+ if (TCGV_EQUAL(dest, src1)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_not_tl(rslt, src1);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ return BS_NONE;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index 916d94e..36ce19b 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -71,3 +71,7 @@ int arc_gen_SEXB(DisasCtxt *c, TCGv dest, TCGv src1);
int arc_gen_SEXW(DisasCtxt *c, TCGv dest, TCGv src1);
int arc_gen_SWAP(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_NEG(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_ABS(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_NOT(DisasCtxt *c, TCGv dest, TCGv src1);
+
--
2.4.9 (Apple Git-60)
- [Qemu-devel] [PATCH RFC v1 00/29] ARC cores, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 02/29] target-arc: ADC, ADD, ADD1, ADD2, ADD3, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 04/29] target-arc: AND, OR, XOR, BIC, TST, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 03/29] target-arc: SUB, SUB1, SUB2, SUB3, SBC, RSUB, CMP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 09/29] target-arc: NEG, ABS, NOT,
Michael Rolnik <=
- [Qemu-devel] [PATCH RFC v1 07/29] target-arc: MAX, MIN, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 01/29] target-arc: initial commit, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 06/29] target-arc: EX, LD, ST, SYNC, PREFETCH, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 05/29] target-arc: ASL(m), ASR(m), LSR(m), ROR(m), Michael Rolnik, 2016/09/08
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