[Qemu-devel] [PATCH RFC v1 03/29] target-arc: SUB, SUB1, SUB2, SUB3, SBC, RSUB, CMP

[Michael Rolnik]

Signed-off-by: Michael Rolnik <address@hidden>
---
 target-arc/translate-inst.c | 165 ++++++++++++++++++++++++++++++++++++++++++++
 target-arc/translate-inst.h |   8 +++
 2 files changed, 173 insertions(+)

diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index 50119bf..7389e5c 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -66,6 +66,44 @@ static void gen_add_Vf(TCGv dest, TCGv src1, TCGv src2)
     tcg_temp_free_i32(t1);
 }
 
+static void gen_sub_Cf(TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv t1 = tcg_temp_new_i32();
+    TCGv t2 = tcg_temp_new_i32();
+    TCGv t3 = tcg_temp_new_i32();
+
+    tcg_gen_not_tl(t1, src1);       /*  t1 = ~src1                          */
+    tcg_gen_and_tl(t2, t1, src2);   /*  t2 = ~src1 & src2                   */
+    tcg_gen_or_tl(t3, t1, src2);    /*  t3 = (~src1 | src2) & dest          */
+    tcg_gen_and_tl(t3, t3, dest);
+    tcg_gen_or_tl(t2, t2, t3);      /*  t2 = ~src1 & src2
+                                           | ~src1 & dest
+                                           | dest & src2                    */
+    tcg_gen_shri_tl(cpu_Cf, t2, 31);/*  Cf = t2(31)                         */
+
+    tcg_temp_free_i32(t3);
+    tcg_temp_free_i32(t2);
+    tcg_temp_free_i32(t1);
+}
+
+static void gen_sub_Vf(TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv t1 = tcg_temp_new_i32();
+    TCGv t2 = tcg_temp_new_i32();
+
+    /*
+        t1 = src1 & ~src2 & ~dest
+           | ~src1 & src2 & dest
+           = (src1 ^ dest) & (src1 ^ dest)*/
+    tcg_gen_xor_tl(t1, src1, dest);
+    tcg_gen_xor_tl(t2, src1, src2);
+    tcg_gen_and_tl(t1, t1, t2);
+    tcg_gen_shri_tl(cpu_Vf, t1, 31);/*  Vf = t1(31) */
+
+    tcg_temp_free_i32(t2);
+    tcg_temp_free_i32(t1);
+}
+
 /*
     ADC
 */
@@ -168,3 +206,130 @@ int arc_gen_ADD3(DisasCtxt *ctx, TCGv dest, TCGv src1, 
TCGv src2)
     return  BS_NONE;
 }
 
+/*
+    SUB
+*/
+int arc_gen_SUB(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_sub_tl(rslt, src1, src2);
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+        gen_sub_Cf(rslt, src1, src2);
+        gen_sub_Vf(rslt, src1, src2);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+
+/*
+    SBC
+*/
+int arc_gen_SBC(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_sub_tl(rslt, src1, src2);
+    tcg_gen_sub_tl(rslt, rslt, cpu_Cf);
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+        gen_sub_Cf(rslt, src1, src2);
+        gen_sub_Vf(rslt, src1, src2);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+/*
+    SUB1
+*/
+int arc_gen_SUB1(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv t0 = tcg_temp_new_i32();
+
+    tcg_gen_shli_tl(t0, src2, 1);
+    arc_gen_SUB(ctx, dest, src1, t0);
+
+    tcg_temp_free_i32(t0);
+
+    return  BS_NONE;
+}
+
+/*
+    SUB2
+*/
+int arc_gen_SUB2(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv t0 = tcg_temp_new_i32();
+
+    tcg_gen_shli_tl(t0, src2, 2);
+    arc_gen_SUB(ctx, dest, src1, t0);
+
+    tcg_temp_free_i32(t0);
+
+    return  BS_NONE;
+}
+
+/*
+    SUB3
+*/
+int arc_gen_SUB3(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv t0 = tcg_temp_new_i32();
+
+    tcg_gen_shli_tl(t0, src2, 3);
+    arc_gen_SUB(ctx, dest, src1, t0);
+
+    tcg_temp_free_i32(t0);
+
+    return  BS_NONE;
+}
+
+/*
+    RSUB
+*/
+int arc_gen_RSUB(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    return arc_gen_SUB(ctx, dest, src2, src1);
+}
+
+/*
+    CMP
+*/
+int arc_gen_CMP(DisasCtxt *ctx, TCGv src1, TCGv src2)
+{
+    TCGv rslt = tcg_temp_new_i32();
+
+    tcg_gen_sub_tl(rslt, src1, src2);
+
+    tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+    tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    gen_sub_Cf(rslt, src1, src2);
+    gen_sub_Vf(rslt, src1, src2);
+
+    tcg_temp_free_i32(rslt);
+
+    return  BS_NONE;
+}
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index 08e23c7..40ed8a0 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -28,3 +28,11 @@ int arc_gen_ADD1(DisasCtxt *c, TCGv dest, TCGv src1, TCGv 
src2);
 int arc_gen_ADD2(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
 int arc_gen_ADD3(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
 
+int arc_gen_SUB(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_SUB1(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_SUB2(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_SUB3(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_SBC(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_RSUB(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_CMP(DisasCtxt *c, TCGv src1, TCGv src2);
+
-- 
2.4.9 (Apple Git-60)