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Re: [Qemu-devel] [PULL 0/7] target-mips queue
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 0/7] target-mips queue |
Date: |
Mon, 10 Nov 2014 15:05:09 +0000 |
On 10 November 2014 14:57, Peter Maydell <address@hidden> wrote:
> Applied, thanks.
PS: you might like to look at suppressing these relatively
new clang warnings:
target-mips/translate.c:1968:15: warning: no case matching constant
switch condition '16'
FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(fp0, fd))
^~~~~
target-mips/translate.c:1885:13: note: expanded from macro 'FOP_CONDNS'
switch (ifmt) { \
^
That can wait for 2.3 though, we have plenty of other clang
warnings still and the code looks correct.
thanks
-- PMM
- [Qemu-devel] [PULL 0/7] target-mips queue, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 1/7] mips: Remove CONFIG_VT82C686 from non-Fulong configs, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 2/7] mips: Respect CP0.Status.CU1 for microMIPS FP branches, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 3/7] mips: Add macros for CP0.Config3 and CP0.Config4 bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 4/7] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 7/7] target-mips: fix multiple TCG registers covering same data, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 6/7] mips: Ensure PC update with MTC0 single-stepping, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 5/7] target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ, Leon Alrae, 2014/11/07
- Re: [Qemu-devel] [PULL 0/7] target-mips queue, Peter Maydell, 2014/11/10
- Re: [Qemu-devel] [PULL 0/7] target-mips queue,
Peter Maydell <=