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Re: [Qemu-devel] [PULL 0/7] target-mips queue
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 0/7] target-mips queue |
Date: |
Mon, 10 Nov 2014 14:57:49 +0000 |
On 7 November 2014 16:56, Leon Alrae <address@hidden> wrote:
> Hi,
>
> A bunch of bug fixes for 2.2, please pull.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <address@hidden>
> Cc: Aurelien Jarno <address@hidden>
>
> The following changes since commit 6e76d125f244e10676b917208f2a074729820246:
>
> Update version for v2.2.0-rc0 release (2014-11-05 15:21:04 +0000)
>
> are available in the git repository at:
>
> git://github.com/lalrae/qemu.git tags/mips-20141107
>
> for you to fetch changes up to cb269f273fdbdb26ddb1cba4a0fe2249418a8e77:
>
> target-mips: fix multiple TCG registers covering same data (2014-11-07
> 14:15:28 +0000)
>
> ----------------------------------------------------------------
> MIPS patches 2014-11-07
>
> Changes:
> * bug fixes
Applied, thanks.
-- PMM
- [Qemu-devel] [PULL 0/7] target-mips queue, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 1/7] mips: Remove CONFIG_VT82C686 from non-Fulong configs, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 2/7] mips: Respect CP0.Status.CU1 for microMIPS FP branches, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 3/7] mips: Add macros for CP0.Config3 and CP0.Config4 bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 4/7] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 7/7] target-mips: fix multiple TCG registers covering same data, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 6/7] mips: Ensure PC update with MTC0 single-stepping, Leon Alrae, 2014/11/07
- [Qemu-devel] [PULL 5/7] target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ, Leon Alrae, 2014/11/07
- Re: [Qemu-devel] [PULL 0/7] target-mips queue,
Peter Maydell <=