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[Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spuriou
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts |
Date: |
Thu, 17 Apr 2014 11:33:56 +0100 |
From: Beniamino Galvani <address@hidden>
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing explicitly the timer
index to the callback function.
Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Li Guang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/timer/allwinner-a10-pit.c | 25 ++++++++++++++-----------
include/hw/timer/allwinner-a10-pit.h | 8 ++++++++
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
index b27fce8..696b7d9 100644
--- a/hw/timer/allwinner-a10-pit.c
+++ b/hw/timer/allwinner-a10-pit.c
@@ -193,18 +193,17 @@ static void a10_pit_reset(DeviceState *dev)
static void a10_pit_timer_cb(void *opaque)
{
- AwA10PITState *s = AW_A10_PIT(opaque);
- uint8_t i;
+ AwA10TimerContext *tc = opaque;
+ AwA10PITState *s = tc->container;
+ uint8_t i = tc->index;
- for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
- if (s->control[i] & AW_A10_PIT_TIMER_EN) {
- s->irq_status |= 1 << i;
- if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
- ptimer_stop(s->timer[i]);
- s->control[i] &= ~AW_A10_PIT_TIMER_EN;
- }
- qemu_irq_pulse(s->irq[i]);
+ if (s->control[i] & AW_A10_PIT_TIMER_EN) {
+ s->irq_status |= 1 << i;
+ if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
+ ptimer_stop(s->timer[i]);
+ s->control[i] &= ~AW_A10_PIT_TIMER_EN;
}
+ qemu_irq_pulse(s->irq[i]);
}
}
@@ -223,7 +222,11 @@ static void a10_pit_init(Object *obj)
sysbus_init_mmio(sbd, &s->iomem);
for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
- bh[i] = qemu_bh_new(a10_pit_timer_cb, s);
+ AwA10TimerContext *tc = &s->timer_context[i];
+
+ tc->container = s;
+ tc->index = i;
+ bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
s->timer[i] = ptimer_init(bh[i]);
ptimer_set_freq(s->timer[i], 240000);
}
diff --git a/include/hw/timer/allwinner-a10-pit.h
b/include/hw/timer/allwinner-a10-pit.h
index 15efab8..a48d3c7 100644
--- a/include/hw/timer/allwinner-a10-pit.h
+++ b/include/hw/timer/allwinner-a10-pit.h
@@ -35,12 +35,20 @@
#define AW_A10_PIT_DEFAULT_CLOCK 0x4
+typedef struct AwA10PITState AwA10PITState;
+
+typedef struct AwA10TimerContext {
+ AwA10PITState *container;
+ int index;
+} AwA10TimerContext;
+
typedef struct AwA10PITState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
qemu_irq irq[AW_A10_PIT_TIMER_NR];
ptimer_state * timer[AW_A10_PIT_TIMER_NR];
+ AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
MemoryRegion iomem;
uint32_t irq_enable;
--
1.9.1
- [Qemu-devel] [PULL 00/51] target-arm queue, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 48/51] misc: zynq_slcr: Make DB_PRINTs always compile, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 49/51] net: cadence_gem: Make phy respond to broadcast, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 47/51] misc: zynq_slcr: Convert SBD::init to object init, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 50/51] arm: translate.c: Fix smlald Instruction, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 51/51] target-arm: A64: fix unallocated test of scalar SQXTUN, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 45/51] allwinner-emac: update irq status after writes to interrupt registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 44/51] allwinner-emac: set autonegotiation complete bit on link up, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 43/51] allwinner-a10-pit: implement prescaler and source selection, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts,
Peter Maydell <=
- [Qemu-devel] [PULL 42/51] allwinner-a10-pit: use level triggered interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 01/51] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 39/51] allwinner-a10-pic: set vector address when an interrupt is pending, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 46/51] misc: zynq-slcr: Rewrite, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 38/51] timer: cadence_ttc: Fix match register write logic, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 37/51] target-arm/gdbstub64.c: remove useless 'break' statement., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 36/51] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 34/51] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 33/51] target-arm: Implement CBAR for Cortex-A57, Peter Maydell, 2014/04/17