[Qemu-devel] [PULL 00/51] target-arm queue

[Peter Maydell]

target-arm pull request for when trunk reopens for 2.1.
This contains mostly the A64 system emulation patchset, and
also some other things that have accumulated during freeze.

thanks
-- PMM

The following changes since commit 851627352c52b5beebf119785885391fa05a44c5:

  Update version for v2.0.0-rc3 release (2014-04-14 17:45:11 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20140417

for you to fetch changes up to 123218cff73573c646af89dfa36662713498fcd0:

  target-arm: A64: fix unallocated test of scalar SQXTUN (2014-04-17 11:21:36 
+0100)

----------------------------------------------------------------
target-arm queue:
 * AArch64 system mode support; this is all the CPU emulation code
   but not the virt board support
 * cadence_ttc match register bugfix
 * Allwinner A10 PIC, PIT and ethernet fixes
 * zynq-slcr rewrite
 * cadence_gem bugfix
 * fix for SMLALD/SMLSLD insn in A32
 * fix for SQXTUN in A64

----------------------------------------------------------------
Alex Bennée (1):
      target-arm: A64: fix unallocated test of scalar SQXTUN

Beniamino Galvani (7):
      allwinner-a10-pic: set vector address when an interrupt is pending
      allwinner-a10-pic: fix behaviour of pending register
      allwinner-a10-pit: avoid generation of spurious interrupts
      allwinner-a10-pit: use level triggered interrupts
      allwinner-a10-pit: implement prescaler and source selection
      allwinner-emac: set autonegotiation complete bit on link up
      allwinner-emac: update irq status after writes to interrupt registers

Chen Gang (1):
      target-arm/gdbstub64.c: remove useless 'break' statement.

Peter Crosthwaite (6):
      timer: cadence_ttc: Fix match register write logic
      misc: zynq-slcr: Rewrite
      misc: zynq_slcr: Convert SBD::init to object init
      misc: zynq_slcr: Make DB_PRINTs always compile
      net: cadence_gem: Make phy respond to broadcast
      arm: translate.c: Fix smlald Instruction

Peter Maydell (32):
      target-arm: Split out private-to-target functions into internals.h
      target-arm: Implement AArch64 DAIF system register
      target-arm: Define exception record for AArch64 exceptions
      target-arm: Provide correct syndrome information for cpreg access traps
      target-arm: Add support for generating exceptions with syndrome 
information
      target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
      target-arm: A64: Add assertion that FP access was checked
      target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1
      target-arm: Don't mention PMU in debug feature register
      target-arm: A64: Implement DC ZVA
      target-arm: Use dedicated CPU state fields for ARM946 access bit registers
      target-arm: Add AArch64 ELR_EL1 register.
      target-arm: Implement SP_EL0, SP_EL1
      target-arm: Implement AArch64 SPSR_EL1
      target-arm: Move arm_log_exception() into internals.h
      target-arm: Implement ARMv8 MVFR registers
      target-arm: Add Cortex-A57 processor
      target-arm: Implement AArch64 views of AArch32 ID registers
      target-arm: Implement AArch64 view of CONTEXTIDR
      target-arm: Implement AArch64 view of ACTLR
      target-arm: Implement ISR_EL1 register
      target-arm: Remove THUMB2EE feature from AArch64 'any' CPU
      target-arm: Don't expose wildcard ID register definitions for ARMv8
      target-arm: Replace wildcarded cpreg definitions with precise ones for 
ARMv8
      target-arm: Implement auxiliary fault status registers
      target-arm: Implement AArch64 address translation operations
      target-arm: Implement RVBAR register
      target-arm: Implement Cortex-A57 implementation-defined system registers
      target-arm: Implement CBAR for Cortex-A57
      target-arm: Make Cortex-A15 CBAR read-only
      target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc
      target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32

Rob Herring (4):
      target-arm: Provide syndrome information for MMU faults
      target-arm: Add v8 mmu translation support
      target-arm: Implement AArch64 views of fault status and data registers
      target-arm: Implement AArch64 EL1 exception handling

 hw/arm/cubieboard.c                  |  13 +
 hw/intc/allwinner-a10-pic.c          |  22 +-
 hw/misc/zynq_slcr.c                  | 697 +++++++++++++-----------------
 hw/net/allwinner_emac.c              |   6 +-
 hw/net/cadence_gem.c                 |   4 +-
 hw/timer/allwinner-a10-pit.c         |  66 ++-
 hw/timer/cadence_ttc.c               |   2 +
 include/exec/softmmu_exec.h          |  52 +++
 include/hw/net/allwinner_emac.h      |   1 +
 include/hw/timer/allwinner-a10-pit.h |   9 +
 linux-user/main.c                    |  56 ++-
 target-arm/cpu-qom.h                 |  10 +-
 target-arm/cpu.c                     |  30 +-
 target-arm/cpu.h                     |  81 ++--
 target-arm/cpu64.c                   | 115 ++++-
 target-arm/gdbstub64.c               |   2 -
 target-arm/helper-a64.c              |  76 ++++
 target-arm/helper.c                  | 810 ++++++++++++++++++++++++++---------
 target-arm/helper.h                  |   7 +-
 target-arm/internals.h               | 267 ++++++++++++
 target-arm/kvm32.c                   |  19 +-
 target-arm/kvm64.c                   |  71 ++-
 target-arm/machine.c                 |  13 +-
 target-arm/op_helper.c               |  92 +++-
 target-arm/translate-a64.c           | 443 +++++++++++++++++--
 target-arm/translate.c               | 229 +++++++---
 target-arm/translate.h               |  23 +-
 27 files changed, 2413 insertions(+), 803 deletions(-)
 create mode 100644 target-arm/internals.h