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[Qemu-devel] [PULL 37/51] target-arm/gdbstub64.c: remove useless 'break'
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 37/51] target-arm/gdbstub64.c: remove useless 'break' statement. |
Date: |
Thu, 17 Apr 2014 11:33:52 +0100 |
From: Chen Gang <address@hidden>
Clean up useless 'break' statement after 'return' statement.
Signed-off-by: Chen Gang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/gdbstub64.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target-arm/gdbstub64.c b/target-arm/gdbstub64.c
index e8a8295..8f3b8d1 100644
--- a/target-arm/gdbstub64.c
+++ b/target-arm/gdbstub64.c
@@ -32,10 +32,8 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t
*mem_buf, int n)
switch (n) {
case 31:
return gdb_get_reg64(mem_buf, env->xregs[31]);
- break;
case 32:
return gdb_get_reg64(mem_buf, env->pc);
- break;
case 33:
return gdb_get_reg32(mem_buf, pstate_read(env));
}
--
1.9.1
- [Qemu-devel] [PULL 51/51] target-arm: A64: fix unallocated test of scalar SQXTUN, (continued)
- [Qemu-devel] [PULL 51/51] target-arm: A64: fix unallocated test of scalar SQXTUN, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 45/51] allwinner-emac: update irq status after writes to interrupt registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 44/51] allwinner-emac: set autonegotiation complete bit on link up, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 43/51] allwinner-a10-pit: implement prescaler and source selection, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 42/51] allwinner-a10-pit: use level triggered interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 01/51] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 39/51] allwinner-a10-pic: set vector address when an interrupt is pending, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 46/51] misc: zynq-slcr: Rewrite, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 38/51] timer: cadence_ttc: Fix match register write logic, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 37/51] target-arm/gdbstub64.c: remove useless 'break' statement.,
Peter Maydell <=
- [Qemu-devel] [PULL 36/51] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 34/51] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 33/51] target-arm: Implement CBAR for Cortex-A57, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 35/51] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 32/51] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 31/51] target-arm: Implement RVBAR register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 29/51] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 30/51] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 40/51] allwinner-a10-pic: fix behaviour of pending register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 27/51] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/04/17