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[Qemu-devel] [PULL 05/45] hw/intc/exynos4210_combiner: Don't overrun out
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/45] hw/intc/exynos4210_combiner: Don't overrun output_irq array in init |
Date: |
Wed, 26 Feb 2014 18:01:55 +0000 |
The Exynos4210 combiner has IIC_NIRQ inputs and IIC_NGRP outputs;
use the correct constant in the loop initializing our output
sysbus IRQs so that we don't overrun the output_irq[] array.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Andreas Färber <address@hidden>
Cc: address@hidden
---
hw/intc/exynos4210_combiner.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
index ef5e8eb..3287479 100644
--- a/hw/intc/exynos4210_combiner.c
+++ b/hw/intc/exynos4210_combiner.c
@@ -418,7 +418,7 @@ static int exynos4210_combiner_init(SysBusDevice *sbd)
qdev_init_gpio_in(dev, exynos4210_combiner_handler, IIC_NIRQ);
/* Connect SysBusDev irqs to device specific irqs */
- for (i = 0; i < IIC_NIRQ; i++) {
+ for (i = 0; i < IIC_NGRP; i++) {
sysbus_init_irq(sbd, &s->output_irq[i]);
}
--
1.9.0
- [Qemu-devel] [PULL 31/45] target-arm: Get MMU index information correct for A64 code, (continued)
- [Qemu-devel] [PULL 31/45] target-arm: Get MMU index information correct for A64 code, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 04/45] target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 24/45] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 33/45] target-arm: Store AIF bits in env->pstate for AArch32, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 17/45] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 27/45] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 30/45] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 29/45] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 34/45] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 15/45] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 05/45] hw/intc/exynos4210_combiner: Don't overrun output_irq array in init,
Peter Maydell <=
- [Qemu-devel] [PULL 20/45] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 14/45] target-arm: Fix raw read and write functions on AArch64 registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 13/45] hw: arm_gic_kvm: Add KVM VGIC save/restore logic, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 28/45] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 26/45] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 08/45] hw/intc/arm_gic: Fix GIC_SET_LEVEL, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 32/45] target-arm: A64: Implement WFI, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 19/45] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 02/45] hw/net/stellaris_enet: Avoid unintended sign extension, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 01/45] hw/misc/arm_sysctl: Fix bad boundary check on mb clock accesses, Peter Maydell, 2014/02/26