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[Qemu-devel] [PULL 17/45] target-arm: Implement AArch64 MIDR_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/45] target-arm: Implement AArch64 MIDR_EL1 |
Date: |
Wed, 26 Feb 2014 18:02:07 +0000 |
Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ff1ed7d..e557533 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1720,6 +1720,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
.type = ARM_CP_OVERRIDE },
+ { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
+ .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
{ .name = "CTR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
--
1.9.0
- [Qemu-devel] [PULL 37/45] include/qemu/crc32c.h: Rename include guards to match filename, (continued)
- [Qemu-devel] [PULL 37/45] include/qemu/crc32c.h: Rename include guards to match filename, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 36/45] target-arm: Add utility function for checking AA32/64 state of an EL, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 38/45] target-arm: Add support for AArch32 ARMv8 CRC32 instructions, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 44/45] dma/pl330: Fix buffer depth, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 35/45] target-arm: Implement AArch64 view of CPACR, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 22/45] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 31/45] target-arm: Get MMU index information correct for A64 code, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 04/45] target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 24/45] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 33/45] target-arm: Store AIF bits in env->pstate for AArch32, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 17/45] target-arm: Implement AArch64 MIDR_EL1,
Peter Maydell <=
- [Qemu-devel] [PULL 27/45] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 30/45] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 29/45] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 34/45] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 15/45] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 05/45] hw/intc/exynos4210_combiner: Don't overrun output_irq array in init, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 20/45] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 14/45] target-arm: Fix raw read and write functions on AArch64 registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 13/45] hw: arm_gic_kvm: Add KVM VGIC save/restore logic, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 28/45] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/02/26