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[Qemu-devel] [PULL 30/45] target-arm: Implement AArch64 OSLAR_EL1 sysreg
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 30/45] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI |
Date: |
Wed, 26 Feb 2014 18:02:20 +0000 |
Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index dde389c..61303b6 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1738,6 +1738,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
+ { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
+ .access = PL1_W, .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
--
1.9.0
- [Qemu-devel] [PULL 38/45] target-arm: Add support for AArch32 ARMv8 CRC32 instructions, (continued)
- [Qemu-devel] [PULL 38/45] target-arm: Add support for AArch32 ARMv8 CRC32 instructions, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 44/45] dma/pl330: Fix buffer depth, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 35/45] target-arm: Implement AArch64 view of CPACR, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 22/45] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 31/45] target-arm: Get MMU index information correct for A64 code, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 04/45] target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 24/45] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 33/45] target-arm: Store AIF bits in env->pstate for AArch32, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 17/45] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 27/45] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 30/45] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI,
Peter Maydell <=
- [Qemu-devel] [PULL 29/45] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 34/45] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 15/45] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 05/45] hw/intc/exynos4210_combiner: Don't overrun output_irq array in init, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 20/45] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 14/45] target-arm: Fix raw read and write functions on AArch64 registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 13/45] hw: arm_gic_kvm: Add KVM VGIC save/restore logic, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 28/45] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 26/45] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 08/45] hw/intc/arm_gic: Fix GIC_SET_LEVEL, Peter Maydell, 2014/02/26