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[Qemu-devel] [PATCH v3 09/31] target-arm: Implement AArch64 SCTLR_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 09/31] target-arm: Implement AArch64 SCTLR_EL1 |
Date: |
Sat, 15 Feb 2014 16:07:02 +0000 |
Implement the AArch64 view of the system control register SCTLR_EL1.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/helper.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 51fa634..74b1122 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -169,7 +169,7 @@ typedef struct CPUARMState {
struct {
uint32_t c0_cpuid;
uint64_t c0_cssel; /* Cache size selection. */
- uint32_t c1_sys; /* System control register. */
+ uint64_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c1_scr; /* secure config register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0e459f1..0a9036a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1948,7 +1948,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
- .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 =
0,
+ .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
cp15.c1_sys),
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
.raw_writefn = raw_write,
--
1.8.5
- [Qemu-devel] [PATCH v3 21/31] target-arm: Implement AArch64 DAIF system register, (continued)
- [Qemu-devel] [PATCH v3 21/31] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 29/31] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 13/31] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 19/31] target-arm: A64: Implement WFI, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 11/31] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 20/31] target-arm: Store AIF bits in env->pstate for AArch32, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 09/31] target-arm: Implement AArch64 SCTLR_EL1,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 10/31] target-arm: Implement AArch64 TCR_EL1, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 12/31] target-arm: Implement AArch64 TTBR*, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 01/31] target-arm: Fix raw read and write functions on AArch64 registers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 17/31] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 24/31] target-arm: Add utility function for checking AA32/64 state of an EL, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 23/31] target-arm: Implement AArch64 view of CPACR, Peter Maydell, 2014/02/15