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Re: [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for condi
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select |
Date: |
Mon, 09 Dec 2013 09:03:14 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 |
On 12/09/2013 04:37 AM, Peter Maydell wrote:
> From: Claudio Fontana <address@hidden>
>
> This patch adds support for the instruction group "C3.5.6
> Conditional select": CSEL, CSINC, CSINV, CSNEG.
>
> Signed-off-by: Claudio Fontana <address@hidden>
> [PMM: Improved code generated in the nomatch case as per RTH suggestions]
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/translate-a64.c | 67
> ++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 10/13] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/09
- Re: [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 07/13] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 06/13] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 02/13] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 13/13] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 09/13] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 03/13] target-arm: A64: add support for ADR and ADRP, Peter Maydell, 2013/12/09
- Re: [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops, Peter Maydell, 2013/12/17