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[Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR |
Date: |
Mon, 9 Dec 2013 12:37:25 +0000 |
From: Alexander Graf <address@hidden>
This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted for new decoder, removed a few temporaries,
fixed the 32bit bug, added checks for more
unallocated cases]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 49 ++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9e11621..7c54a82 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -704,10 +704,55 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
unsupported_encoding(s, insn);
}
-/* Extract */
+/* C3.4.3 Extract
+ * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
+ * +----+------+-------------+---+----+------+--------+------+------+
+ * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
+ * +----+------+-------------+---+----+------+--------+------+------+
+ */
static void disas_extract(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
+
+ sf = extract32(insn, 31, 1);
+ n = extract32(insn, 22, 1);
+ rm = extract32(insn, 16, 5);
+ imm = extract32(insn, 10, 6);
+ rn = extract32(insn, 5, 5);
+ rd = extract32(insn, 0, 5);
+ op21 = extract32(insn, 29, 2);
+ op0 = extract32(insn, 21, 1);
+ bitsize = sf ? 64 : 32;
+
+ if (sf != n || op21 || op0 || imm >= bitsize) {
+ unallocated_encoding(s);
+ } else {
+ TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
+
+ tcg_rd = cpu_reg(s, rd);
+
+ if (imm) {
+ /* OPTME: we can special case rm==rn as a rotate */
+ tcg_rm = read_cpu_reg(s, rm, sf);
+ tcg_rn = read_cpu_reg(s, rn, sf);
+ tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
+ tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
+ tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
+ if (!sf) {
+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+ }
+ } else {
+ /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
+ * so an extract from bit 0 is a special case.
+ */
+ if (sf) {
+ tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
+ } else {
+ tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
+ }
+ }
+
+ }
}
/* C3.4 Data processing - immediate */
--
1.8.5
- [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 10/13] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 07/13] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 06/13] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 02/13] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/09