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[Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS insn |
Date: |
Mon, 9 Dec 2013 12:37:33 +0000 |
From: Claudio Fontana <address@hidden>
this patch adds support for the CLS instruction.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/helper-a64.c | 10 ++++++++++
target-arm/helper-a64.h | 2 ++
target-arm/translate-a64.c | 20 +++++++++++++++++++-
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index cccaac6..d3f7067 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -50,6 +50,16 @@ uint64_t HELPER(clz64)(uint64_t x)
return clz64(x);
}
+uint64_t HELPER(cls64)(uint64_t x)
+{
+ return clrsb64(x);
+}
+
+uint32_t HELPER(cls32)(uint32_t x)
+{
+ return clrsb32(x);
+}
+
uint64_t HELPER(rbit64)(uint64_t x)
{
/* assign the correct byte position */
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index 9959139..a163a94 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -19,4 +19,6 @@
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(cls64, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(cls32, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 045a25e..d9bf706 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1114,6 +1114,24 @@ static void handle_clz(DisasContext *s, unsigned int sf,
}
}
+static void handle_cls(DisasContext *s, unsigned int sf,
+ unsigned int rn, unsigned int rd)
+{
+ TCGv_i64 tcg_rd, tcg_rn;
+ tcg_rd = cpu_reg(s, rd);
+ tcg_rn = cpu_reg(s, rn);
+
+ if (sf) {
+ gen_helper_cls64(tcg_rd, tcg_rn);
+ } else {
+ TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn);
+ gen_helper_cls32(tcg_tmp32, tcg_tmp32);
+ tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
+ tcg_temp_free_i32(tcg_tmp32);
+ }
+}
+
static void handle_rbit(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
{
@@ -1236,7 +1254,7 @@ static void disas_data_proc_1src(DisasContext *s,
uint32_t insn)
handle_clz(s, sf, rn, rd);
break;
case 5: /* CLS */
- unsupported_encoding(s, insn);
+ handle_cls(s, sf, rn, rd);
break;
}
}
--
1.8.5
- [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 10/13] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS insn,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 07/13] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 06/13] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 02/13] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 13/13] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 09/13] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 03/13] target-arm: A64: add support for ADR and ADRP, Peter Maydell, 2013/12/09
- Re: [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops, Peter Maydell, 2013/12/17