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[Qemu-devel] [RFC PATCH 09/21] target-arm: adjust SCR CP15 register acce
From: |
Sergey Fedorov |
Subject: |
[Qemu-devel] [RFC PATCH 09/21] target-arm: adjust SCR CP15 register access rights |
Date: |
Tue, 03 Dec 2013 12:48:43 +0400 |
SCR register is accessible in PL3 (secure privileged) mode only. Fix SRC
access rights since arm_current_pl() can return PL3 now.
Signed-off-by: Sergey Fedorov <address@hidden>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e406ec9..3bd0a64 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1530,7 +1530,7 @@ static int vbar_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static const ARMCPRegInfo tz_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
+ .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
.resetvalue = 0 },
{ .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
--
1.7.9.5
[Qemu-devel] [RFC PATCH 09/21] target-arm: adjust SCR CP15 register access rights,
Sergey Fedorov <=
[Qemu-devel] [RFC PATCH 14/21] target-arm: split TLB for secure state, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 08/21] target-arm: adjust arm_current_pl() for TrustZone, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 01/21] target-arm: add TrustZone CPU feature, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode, Sergey Fedorov, 2013/12/03