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[Qemu-devel] [RFC PATCH 10/21] target-arm: add non-secure Translation Bl
From: |
Sergey Fedorov |
Subject: |
[Qemu-devel] [RFC PATCH 10/21] target-arm: add non-secure Translation Block flag |
Date: |
Tue, 03 Dec 2013 12:48:44 +0400 |
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter <address@hidden>.
This flag prevents from executing TCG code generated for other CPU
secure state. It also allows to generate different TCG code depending on
CPU secure state.
Signed-off-by: Sergey Fedorov <address@hidden>
---
target-arm/cpu.h | 7 +++++++
target-arm/translate.c | 3 +++
target-arm/translate.h | 1 +
3 files changed, 11 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1b03450..f47dbdf 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -854,6 +854,8 @@ static inline int cpu_mmu_index (CPUARMState *env)
#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
+#define ARM_TBFLAG_NS_SHIFT 17
+#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
/* Bit usage when in AArch64 state: currently no bits defined */
@@ -874,6 +876,8 @@ static inline int cpu_mmu_index (CPUARMState *env)
(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
#define ARM_TBFLAG_BSWAP_CODE(F) \
(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
+#define ARM_TBFLAG_NS(F) \
+ (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
@@ -897,6 +901,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
if (privmode) {
*flags |= ARM_TBFLAG_PRIV_MASK;
}
+ if (!arm_is_secure(env)) {
+ *flags |= ARM_TBFLAG_NS_MASK;
+ }
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
*flags |= ARM_TBFLAG_VFPEN_MASK;
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 665c8ac..a47fcdb 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -52,8 +52,10 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
+#define IS_NS(s) 1
#else
#define IS_USER(s) (s->user)
+#define IS_NS(s) (s->ns)
#endif
/* These instructions trap after executing, so defer them until after the
@@ -10036,6 +10038,7 @@ static inline void
gen_intermediate_code_internal(ARMCPU *cpu,
dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
#if !defined(CONFIG_USER_ONLY)
dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
+ dc->ns = ARM_TBFLAG_NS(tb->flags);
#endif
dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 67c7760..05b4f34 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -19,6 +19,7 @@ typedef struct DisasContext {
int bswap_code;
#if !defined(CONFIG_USER_ONLY)
int user;
+ int ns;
#endif
int vfp_enabled;
int vec_len;
--
1.7.9.5
[Qemu-devel] [RFC PATCH 09/21] target-arm: adjust SCR CP15 register access rights, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 14/21] target-arm: split TLB for secure state, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 08/21] target-arm: adjust arm_current_pl() for TrustZone, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 01/21] target-arm: add TrustZone CPU feature, Sergey Fedorov, 2013/12/03